公开(公告)号：US20170075658A1

公开(公告)日：2017-03-16

申请号：US15262168

申请日：2016-09-12

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract translation: 方法和领先的零预测器，用于估计固定点算术运算结果中的前导零数，这对任何带符号的固定点数都精确到一位以内。 前置零预测器包括输入编码电路，其从固定点数生成编码输入串; 基于窗口的代理串生成电路，其生成代数串，其前导码是通过检查编码输入串的连续窗口并设置代理串的相应位的算术运算结果中的前导码的估计值， 考试; 以及计数器电路，被配置为基于所述替代串中的前一个来估计所述算术运算结果中的前导零的数目。

公开(公告)号：US20230305812A1

公开(公告)日：2023-09-28

申请号：US18204872

申请日：2023-06-01

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US10346137B2

公开(公告)日：2019-07-09

申请号：US16152021

申请日：2018-10-04

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US10949169B2

公开(公告)日：2021-03-16

申请号：US16789390

申请日：2020-02-12

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20200183651A1

公开(公告)日：2020-06-11

申请号：US16789390

申请日：2020-02-12

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US11669305B2

公开(公告)日：2023-06-06

申请号：US17187120

申请日：2021-02-26

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20210182028A1

公开(公告)日：2021-06-17

申请号：US17187120

申请日：2021-02-26

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US20190034171A1

公开(公告)日：2019-01-31

申请号：US16152021

申请日：2018-10-04

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US12141548B2

公开(公告)日：2024-11-12

申请号：US18204872

申请日：2023-06-01

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US10698660B2

公开(公告)日：2020-06-30

申请号：US16429869

申请日：2019-06-03

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.