公开(公告)号：US06214676B1

公开(公告)日：2001-04-10

申请号：US09506840

申请日：2000-02-18

申请人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

发明人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/11

摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.

摘要翻译： 具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。 存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。 根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。 在第一区域上形成第一栅电极。 掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。 第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。 此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。 金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。

公开(公告)号：US6043537A

公开(公告)日：2000-03-28

申请号：US016092

申请日：1998-01-30

申请人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

发明人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

IPC分类号： H01L27/10 ,  H01L21/8229 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/01

CPC分类号： H01L27/10894 ,  H01L27/11 ,  H01L27/10873 ,  H01L27/10888

摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.

摘要翻译： 具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。 存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。 根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。 在第一区域上形成第一栅电极。 掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。 第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。 此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。 金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。