公开(公告)号：US06683666B1

公开(公告)日：2004-01-27

申请号：US09709312

申请日：2000-11-13

申请人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

发明人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

IPC分类号： G02F11335

CPC分类号： G02F1/133555 ,  G02F1/136227

摘要： The present invention provide a reflective transmission type TFT LCD wherein each of the reflective pixel electrode and the transmissive pixel electrode is connected directly to a source electrode of a thin film transistor, or the transmissive pixel electrode are concurrently formed with gate electrode and made with double layer of transparent conduction layer and metal layer which can be used as parameter conduction layer between the transparent conduction layer and the reflective pixel electrode.

摘要翻译： 本发明提供了一种反射透射型TFT LCD，其中反射像素电极和透射像素电极中的每一个直接连接到薄膜晶体管的源电极，或者透射像素电极同时由栅电极形成并制成双 透明导电层和金属层的层，其可以用作透明导电层和反射像素电极之间的参数传导层。

公开(公告)号：US06469759B2

公开(公告)日：2002-10-22

申请号：US09966090

申请日：2001-10-01

申请人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

发明人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

IPC分类号： G02F11335

CPC分类号： G02F1/133553 ,  G02F1/136227

摘要： A reflection type liquid crystal display device having a reflection electrode with an enhanced reflectivity and a method for fabricating the same includes a dimple on a convex of the reflection electrode. The method for fabricating such a reflection type liquid crystal display uses a photo-sensitive organic insulation film to form bumps for the convex-concave structure, thus increases only the number of times of exposures, thereby simplifying the overall process.

摘要翻译： 具有增强的反射率的反射电极的反射型液晶显示装置及其制造方法包括在反射电极的凸起上的凹坑。 制造这种反射型液晶显示器的方法使用光敏有机绝缘膜来形成用于凸凹结构的凸块，从而仅增加曝光次数，从而简化了整体处理。

公开(公告)号：US5981324A

公开(公告)日：1999-11-09

申请号：US956584

申请日：1997-10-23

申请人： Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

发明人： Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

IPC分类号： H01L21/8239 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/1052

摘要： Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.

摘要翻译： 形成其中具有存储单元阵列的集成电路及其外围电路的方法包括以下步骤：为存储单元阵列中的晶体管选择性地形成更多的轻掺杂源极和漏极区域。 这些更轻掺杂的源极和漏极区域被设计为在离子注入中具有较少的晶体缺陷，使得与其耦合的存储电容器具有改善的刷新特性。 优选的方法包括以下步骤：在半导体衬底的存储单元部分中形成第一导电类型的第一阱区域（例如，P型）和在半导体衬底延伸的外围电路部分中的第一导电类型的第二阱区域 邻近存储单元部分。 然后使用常规技术分别在第一和第二阱区上形成第一和第二绝缘栅电极。 然后使用第一和第二绝缘栅电极作为植入掩模，将第一导电类型的第一掺杂剂以第一剂量水平注入第一阱区和第二阱区。 然后这些掺杂剂被扩散以形成与第一和第二绝缘栅电极相邻的轻掺杂源极和漏极区。 然后使用自对准技术将第二导电类型的第二掺杂剂以大于第一剂量水平的第二剂量水平选择性地植入第二阱区。 然而，这些掺杂剂优选不被植入第一阱区。 然后将这些第二掺杂剂扩散到第二源/漏区。

公开(公告)号：US5210056A

公开(公告)日：1993-05-11

申请号：US799052

申请日：1991-11-27

申请人： Chil-kun Pong ,  Myeon-koo Kang ,  Yang-koo Lee ,  Dong-ho Shin

发明人： Chil-kun Pong ,  Myeon-koo Kang ,  Yang-koo Lee ,  Dong-ho Shin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/306 ,  H01L21/316

CPC分类号： H01L21/28185 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/28211 ,  Y10S438/906 ,  Y10S438/981

摘要： A fabrication method of a semiconductor device is disclosed. Particularly, in the process of forming a gate oxide film on a semiconductor substrate, the method for forming a gate oxide film of a semiconductor device comprises the steps of first-annealing the semiconductor substrate in a nitrogen (N.sub.2) atmosphere; forming a gate oxide film by wet-oxidizing the annealed semiconductor substrate at a low temperature in a mixed gas atmosphere of oxygen (O.sub.2) and hydrogen (H.sub.2); and second-annealing the semiconductor substrate where gate oxide film has been formed, at a high temperature in a nitrogen (N.sub.2) atmosphere. Accordingly, the thinning phenomenon of the gate oxide film near the field oxide film is prevented and the instability such V.sub.FB in the conventional field oxidation method is considerably recovered. Also, the field concentration phenomenon is decreased and tolerance to dielectric breakdown is increased.

摘要翻译： 公开了一种半导体器件的制造方法。 特别是在半导体衬底上形成栅氧化膜的工艺中，形成半导体器件的栅极氧化膜的方法包括以下步骤：在氮（N 2）气氛中对半导体衬底进行退火; 通过在氧气（O 2）和氢气（H 2）的混合气体气氛中在低温下对退火的半导体衬底进行湿氧化来形成栅氧化膜; 并在氮（N 2）气氛中在高温下对形成有栅极氧化膜的半导体衬底进行二次退火。 因此，防止了场氧化膜附近的栅极氧化膜的稀化现象，并且在常规场氧化法中的这种VFB的不稳定性被大大地恢复。 此外，场浓度现象降低，并且介电击穿的耐受性增加。

公开(公告)号：US06342935B1

公开(公告)日：2002-01-29

申请号：US09435356

申请日：1999-11-08

申请人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

发明人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

IPC分类号： G02F11335

CPC分类号： G02F1/133553 ,  G02F1/136227

摘要： A reflection type liquid crystal display device having a reflection electrode with an enhanced reflectivity and a method for fabricating the same includes a dimple on a convex of the reflection electrode. The method for fabricating such a reflection type liquid crystal display uses a photo-sensitive organic insulation film to form bumps for the convex-concave structure, thus increases only the number of times of exposures, thereby simplifying the overall process.

摘要翻译： 具有增强的反射率的反射电极的反射型液晶显示装置及其制造方法包括在反射电极的凸起上的凹坑。 制造这种反射型液晶显示器的方法使用光敏有机绝缘膜来形成用于凸凹结构的凸块，从而仅增加曝光次数，从而简化了整体处理。

公开(公告)号：US06214676B1

公开(公告)日：2001-04-10

申请号：US09506840

申请日：2000-02-18

申请人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

发明人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/11

摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.

摘要翻译： 具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。 存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。 根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。 在第一区域上形成第一栅电极。 掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。 第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。 此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。 金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。

公开(公告)号：US07068335B2

公开(公告)日：2006-06-27

申请号：US10761414

申请日：2004-01-22

申请人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

发明人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Myeon-Koo Kang

IPC分类号： G02F1/1335

CPC分类号： G02F1/133555 ,  G02F1/136227

摘要： The present invention provide a reflective-transmission type TFT LCD wherein each of the reflective pixel electrode and the transmissive pixel electrode is connected directly to a source electrode of a thin film transistor, or the transmissive pixel electrode are concurrently formed with gate electrode and made with double layer of transparent conduction layer and metal layer which can be used as parameter conduction layer between the transparent conduction layer and the reflective pixel electrode. According to one aspect of the present invention, the reflective transmission type thin film transistor liquid crystal display (TFT LCD) comprises a glass substrate, at least one thin film transistor on the substrate for controlling a pixel, passivation layer having at least one contact hole in a source region of the thin film transistor, a transmissive pixel electrode which is formed on the passivation layer and is connected with a source electrode of the source region through a contact hole, a reflective pixel electrode which is formed on the passivation layer and is connected with the source electrode of the source region through a contact hole. And the pixel area is composed of a transparent area in which only the transmissive pixel electrode of whole pixel electrode exist and a reflective area in which the reflective pixel electrode exist.

摘要翻译： 本发明提供了一种反射透射型TFT LCD，其中反射像素电极和透射像素电极中的每一个直接连接到薄膜晶体管的源电极，或者透射像素电极同时由栅电极形成并由 双层透明导电层和金属层，可用作透明导电层和反射像素电极之间的参数传导层。 根据本发明的一个方面，反射透射型薄膜晶体管液晶显示器（TFT LCD）包括玻璃基板，用于控制像素的基板上的至少一个薄膜晶体管，具有至少一个接触孔 在薄膜晶体管的源极区域中，形成在钝化层上并通过接触孔与源极区域的源极连接的透射像素电极，形成在钝化层上的反射像素电极，并且是 通过接触孔与源极区域的源极连接。 并且像素区域由仅存在整个像素电极的透射像素电极和存在反射像素电极的反射区域的透明区域组成。

公开(公告)号：US06522375B1

公开(公告)日：2003-02-18

申请号：US09519997

申请日：2000-03-06

申请人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Jih-Oh Kwag ,  Myeon-Koo Kang ,  Jong-Eup Shin

发明人： Yong-Kyu Jang ,  Young-Kuil Joo ,  Jih-Oh Kwag ,  Myeon-Koo Kang ,  Jong-Eup Shin

IPC分类号： G02F11343

CPC分类号： G02F1/133553

摘要： Disclosed is a reflection type liquid crystal display and a method for fabricating the same. The reflection type liquid crystal display comprises a reflection electrode of which surface has a plurality of irregular and convex polygons, widths of respective ravines between the convex polygons being constant. Thus, since sizes and heights of the convex polygons are irregular in all directions and flat regions corresponding to the ravines are highly decreased, light reflectivity is enhanced and misalignment of liquid crystal molecules is minimized.

摘要翻译： 公开了一种反射型液晶显示器及其制造方法。 反射型液晶显示器包括表面具有多个不规则和凸形多边形的反射电极，凸多边形之间的各个沟槽的宽度是恒定的。 因此，由于凸多边形的尺寸和高度在所有方向上是不规则的，并且对应于沟槽的平坦区域被高度减小，所以光反射率增加并且液晶分子的未对准被最小化。

公开(公告)号：US6043537A

公开(公告)日：2000-03-28

申请号：US016092

申请日：1998-01-30

申请人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

发明人： In-kyun Jun ,  Young-pil Kim ,  Hyung-moo Park ,  Myeon-koo Kang

IPC分类号： H01L27/10 ,  H01L21/8229 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/01

CPC分类号： H01L27/10894 ,  H01L27/11 ,  H01L27/10873 ,  H01L27/10888

摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.

摘要翻译： 具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。 存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。 根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。 在第一区域上形成第一栅电极。 掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。 第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。 此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。 金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。