公开(公告)号：US20210197023A1

公开(公告)日：2021-07-01

申请号：US16843849

申请日：2020-04-08

Applicant: Industrial Technology Research Institute

Inventor： Min-Hsiung Liang ,  Yun-Yi Huang ,  Tzu-Yang Ting ,  Yu-Jhen Yang ,  Tzu-Hao Yu

IPC: A63B24/00

Abstract: An exercise sensing method, an exercise sensing apparatus and an exercise sensing system are provided. The exercise sensing system includes a computing device, a storage device and at least one biophysical quantity sensor disposed on at least one muscle portion of a user. In the method, a current muscle strength of the muscle portion when the user performs an exercise is monitored by the biophysical quantity sensor. An exercise history of the user is accessed to obtain a muscle strength reference value of the muscle portion when the user previously performed the exercise. The current muscle strength is compared with the muscle strength reference value so as to adjust an exercise intensity of the exercise.

公开(公告)号：US11565152B2

公开(公告)日：2023-01-31

申请号：US16843849

申请日：2020-04-08

Applicant: Industrial Technology Research Institute

Inventor： Min-Hsiung Liang ,  Yun-Yi Huang ,  Tzu-Yang Ting ,  Yu-Jhen Yang ,  Tzu-Hao Yu

IPC: A63B24/00 ,  G16H20/30

Abstract: An exercise sensing method, an exercise sensing apparatus and an exercise sensing system are provided. The exercise sensing system includes a computing device, a storage device and at least one biophysical quantity sensor disposed on at least one muscle portion of a user. In the method, a current muscle strength of the muscle portion when the user performs an exercise is monitored by the biophysical quantity sensor. An exercise history of the user is accessed to obtain a muscle strength reference value of the muscle portion when the user previously performed the exercise. The current muscle strength is compared with the muscle strength reference value so as to adjust an exercise intensity of the exercise.

公开(公告)号：US20180122694A1

公开(公告)日：2018-05-03

申请号：US15597124

申请日：2017-05-16

Applicant: Industrial Technology Research Institute

Inventor： Chun-Yi Cheng ,  Wei-Yuan Cheng ,  Shu-Wei Kuo ,  Yu-Jhen Yang

IPC: H01L21/768 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/3107 ,  H01L21/02172 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.

公开(公告)号：US10522438B2

公开(公告)日：2019-12-31

申请号：US15597124

申请日：2017-05-16

Applicant: Industrial Technology Research Institute

Inventor： Chun-Yi Cheng ,  Wei-Yuan Cheng ,  Shu-Wei Kuo ,  Yu-Jhen Yang

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.