公开(公告)号：US11909405B1

公开(公告)日：2024-02-20

申请号：US18151861

申请日：2023-01-09

申请人： Infineon Technologies AG

发明人： Luigi Grimaldi ,  Thomas Bauernfeind ,  Dmytro Cherniak ,  Fabio Versolatto ,  Andrew Wightwick ,  Fabio Padovan ,  Giovanni Boi

IPC分类号： H03L7/093 ,  H03L7/18 ,  H03L7/099

CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/18

摘要： A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.