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公开(公告)号：US20240080032A1
公开(公告)日：2024-03-07
申请号：US17903238
申请日：2022-09-06
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Thomas Bauernfeind , Thorsten Brandt , Bernhard Greslehner-Nimmervoll , Daniel Maier , Francesco Lombardo , Nicolo Guarducci
CPC classification number: H03L7/0992 , G01S13/343 , H03L7/091
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
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Patent Agency Ranking
公开(公告)号：US20240077579A1
公开(公告)日：2024-03-07
申请号：US18066029
申请日：2022-12-14
Applicant: Infineon Technologies AG
Inventor： Thomas Bauernfeind , Andreas Schwarz , Nicolo Guarducci , Thorsten Brandt , Francesco Lombardo , Bernhard Greslehner-Nimmervoll , Daniel Maier
IPC: G01S7/35
CPC classification number: G01S7/352
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.
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公开(公告)号：US12249998B2
公开(公告)日：2025-03-11
申请号：US17903238
申请日：2022-09-06
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Thomas Bauernfeind , Thorsten Brandt , Bernhard Greslehner-Nimmervoll , Daniel Maier , Francesco Lombardo , Nicolo Guarducci
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
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公开(公告)号：US11909405B1
公开(公告)日：2024-02-20
申请号：US18151861
申请日：2023-01-09
Applicant: Infineon Technologies AG
Inventor： Luigi Grimaldi , Thomas Bauernfeind , Dmytro Cherniak , Fabio Versolatto , Andrew Wightwick , Fabio Padovan , Giovanni Boi
Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.
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公开(公告)号：US11831325B2
公开(公告)日：2023-11-28
申请号：US17579022
申请日：2022-01-19
Applicant: Infineon Technologies AG
Inventor： Matthias Wagner , Thomas Bauernfeind , Oliver Lang
CPC classification number: H03M1/1023 , H03M1/16 , H03M1/44 , H03M1/0695
Abstract: A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.
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公开(公告)号：US20230231568A1
公开(公告)日：2023-07-20
申请号：US17579022
申请日：2022-01-19
Applicant: Infineon Technologies AG
Inventor： Matthias Wagner , Thomas Bauernfeind , Oliver Lang
IPC: H03M1/10
CPC classification number: H03M1/1023
Abstract: A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.
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