公开(公告)号：US20240332283A1

公开(公告)日：2024-10-03

申请号：US18191596

申请日：2023-03-28

Applicant: Infineon Technologies AG

Inventor： Christian Cornelius Russ ,  Gabriel-Dumitru Cretu ,  Filippo Magrini ,  Markus Eckinger ,  Chi Dong Nguyen

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: A silicon controlled rectifier (SCR) includes a first p-well region, a second p-well region, and an n-doped region. The first p-well region is coupled to a first trigger terminal via a first p-doped tap region disposed in the first p-well region. The first p-doped tap region has a higher concentration of a p-type dopant than the first p-well region. The second p-well region is coupled to a second trigger terminal via a second p-doped tap region disposed in the second p-well region. The second p-doped tap region has a higher concentration of a p-type dopant than the second p-well region.

公开(公告)号：US10957792B2

公开(公告)日：2021-03-23

申请号：US16103160

申请日：2018-08-14

Applicant: Infineon Technologies AG

Inventor： Chi Dong Nguyen ,  Andreas Rupp

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm−3 under the majority of the source region. Additional semiconductor device embodiments and methods of manufacture are described.

公开(公告)号：US20200058787A1

公开(公告)日：2020-02-20

申请号：US16103160

申请日：2018-08-14

Applicant: Infineon Technologies AG

Inventor： Chi Dong Nguyen ,  Andreas Rupp

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225

Abstract: A semiconductor device includes a body region of a second conductivity type, a body contact region of the second conductivity type formed in the body region and having a higher average doping concentration than the body region, a source region of a first conductivity type opposite the second conductivity type formed in the body region adjacent the body contact region, a drift zone of the first conductivity type spaced apart from the source region by a section of the body region which forms a channel region of the semiconductor device, and a gate electrode configured to control the channel region. The body contact region extends under a majority of the source region in a direction towards the channel region and has a doping concentration of at least 1e18 cm−3 under the majority of the source region, Additional semiconductor device embodiments and methods of manufacture are described.

公开(公告)号：US20230246068A1

公开(公告)日：2023-08-03

申请号：US18099543

申请日：2023-01-20

Applicant: Infineon Technologies AG

Inventor： Chi Dong Nguyen ,  Till Schlösser

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/407 ,  H01L29/1095 ,  H01L29/7816

Abstract: A field effect transistor, FET, is proposed. The FET includes a source region of a first conductivity type that is electrically connected to a source electrode at a first surface of a semiconductor body. The FET further includes a drain region of the first conductivity type that is electrically connected to a drain electrode at the first surface. A dielectric structure is arranged between the source region and the drain region along a first lateral direction. The dielectric structure includes a gate dielectric on the first surface and a field dielectric structure having a bottom side below the first surface. The FET further includes a gate electrode on the gate dielectric. The gate electrode and the field dielectric structure are spaced from each other along the first lateral direction. The FET further includes a field electrode having a bottom side below a top side of the field dielectric structure.