公开(公告)号：US20230298956A1

公开(公告)日：2023-09-21

申请号：US18119118

申请日：2023-03-08

Applicant: Infineon Technologies AG

Inventor： Chii Shang HONG ,  Li Fong CHONG ,  Yee Beng DARYL YEOW ,  Edward FÜRGUT ,  Mei Fen HIEW ,  Azlina KASSIM ,  Ralf OTREMBA ,  Bernd SCHMOELZER ,  Joon Shyan TAN ,  Lee Shuang WANG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L24/40 ,  H01L24/48 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49558 ,  H01L23/49562 ,  H01L21/565 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2224/40257 ,  H01L2224/48257 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.