公开(公告)号：US20230230903A1

公开(公告)日：2023-07-20

申请号：US18085746

申请日：2022-12-21

Applicant: Infineon Technologies AG

Inventor： Hooi Boon TEOH ,  Hao ZHUANG ,  Oliver BLANK ,  Paul Armand CALO ,  Markus DINKEL ,  Josef Höglauer ,  Daniel Hölzl ,  Wee Aun JASON LIM ,  Gerhard Thomas Nöbauer ,  Ralf OTREMBA ,  Martin Pölzl ,  Ying Pok SAM ,  Xaver Schlögel ,  Chee Voon TAN

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L24/05 ,  H01L24/03 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/291 ,  H01L24/29 ,  H01L2224/26145 ,  H01L2224/04026 ,  H01L2224/0361 ,  H01L2224/83801

Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

公开(公告)号：US20230298956A1

公开(公告)日：2023-09-21

申请号：US18119118

申请日：2023-03-08

Applicant: Infineon Technologies AG

Inventor： Chii Shang HONG ,  Li Fong CHONG ,  Yee Beng DARYL YEOW ,  Edward FÜRGUT ,  Mei Fen HIEW ,  Azlina KASSIM ,  Ralf OTREMBA ,  Bernd SCHMOELZER ,  Joon Shyan TAN ,  Lee Shuang WANG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L24/40 ,  H01L24/48 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49558 ,  H01L23/49562 ,  H01L21/565 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2224/40257 ,  H01L2224/48257 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

公开(公告)号：US20160035665A1

公开(公告)日：2016-02-04

申请号：US14450300

申请日：2014-08-04

Applicant: Infineon Technologies AG

Inventor： Ralf OTREMBA ,  Klaus SCHIESS ,  Anton MAUDER

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49844 ,  H01L23/3114 ,  H01L23/3121 ,  H01L25/072 ,  H01L2924/0002 ,  H02M1/088 ,  H01L2924/00

Abstract: A circuit arrangement is provided, which may include: an embedding package chip carrier; a first chip and a second chip arranged over the embedding package chip carrier, each of the first chip and the second chip comprising: a control terminal, a first controlled terminal, and a second controlled terminal, wherein the control terminal and the first controlled terminal are arranged on a first side of the chip, and wherein the second controlled terminal is arranged on a second side of the chip, wherein the second side is opposite the first side; wherein the first chip is arranged on the embedding package chip carrier such that its first side is facing towards the embedding package chip carrier; and wherein the second chip is arranged on the embedding package chip carrier such that its first side is facing away from the embedding package chip carrier.

Abstract translation: 提供一种电路装置，其可包括：嵌入式封装芯片载体; 布置在所述嵌入式封装芯片载体上的第一芯片和第二芯片，所述第一芯片和所述第二芯片中的每一个包括：控制端子，第一受控端子和第二受控端子，其中所述控制端子和所述第一受控端子 布置在所述芯片的第一侧上，并且其中所述第二受控端子布置在所述芯片的第二侧上，其中所述第二侧与所述第一侧相对; 其中所述第一芯片布置在所述嵌入式封装芯片载体上，使得其第一侧面向所述嵌入封装芯片载体; 并且其中所述第二芯片布置在所述嵌入式封装芯片载体上，使得其第一侧面朝向远离所述嵌入封装芯片载体。

公开(公告)号：US20220173023A1

公开(公告)日：2022-06-02

申请号：US17502156

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Ralf OTREMBA

IPC: H01L23/495

Abstract: A package is disclosed. In one example, the package comprises a first load terminal, a second load terminal, a power component mounted on the first load terminal, and a logic component electrically conductively mounted on one of the first load terminal. The logic component is the second load terminal and electrically connected with the power component for controlling the power component.

公开(公告)号：US20170278762A1

公开(公告)日：2017-09-28

申请号：US15468045

申请日：2017-03-23

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Oliver HAEBERLEN ,  Matteo-Alessandro KUTSCHAK ,  Ralf OTREMBA ,  Petteri PALM ,  Boris PLIKAT ,  Thorsten SCHARF ,  Klaus SCHIESS ,  Fabian SCHNOY ,  Erich SYRI

IPC: H01L21/66 ,  H01L23/498 ,  G01N21/84 ,  H01L23/31

CPC classification number: H01L22/32 ,  G01N21/84 ,  G01N21/95684 ,  G01N2201/12 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/052 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1033

Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.