公开(公告)号：US11217529B2

公开(公告)日：2022-01-04

申请号：US16592156

申请日：2019-10-03

Applicant: Infineon Technologies AG

Inventor： Stefan Beyer ,  Marius Aurel Bodea ,  Jia Yi Wong

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

公开(公告)号：US20190043982A1

公开(公告)日：2019-02-07

申请号：US16050950

申请日：2018-07-31

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Marius Aurel Bodea

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

Abstract: Disclosed are a transistor device and a method. The transistor device includes a semiconductor body with a first surface, an inner region, and an edge region, a drift region of a first doping type in the inner region and the edge region, a plurality of transistor cells in the inner region, and a termination structure in the edge region. The termination structure includes a recess extending from the first surface in the edge region into the semiconductor body, and a floating compensation region with dopant atoms of a second doping type complementary to the first doping type in the drift region adjacent the recess.

公开(公告)号：US10896887B2

公开(公告)日：2021-01-19

申请号：US16295856

申请日：2019-03-07

Applicant: Infineon Technologies AG

Inventor： Marius Aurel Bodea ,  Terry Richard Heidmann ,  Marianne Mataln ,  Claudia Sgiarovello

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.