公开(公告)号：US20160035834A1

公开(公告)日：2016-02-04

申请号：US14447174

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Dorin Ioan Mohai ,  Ilie-Ionut Cristea ,  Adrian Finney ,  Bogdan-Eugen Matei ,  Andrei Cobzaru

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L27/0716 ,  H01L29/0603 ,  H01L29/7395 ,  H03K17/00 ,  H03K17/18

Abstract: A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased.

Abstract translation: 半导体器件包括掺杂有第一类型的掺杂剂的半导体衬底和由一个或多个晶体管单元组成的垂直晶体管。 每个晶体管单元具有形成在衬底中并掺杂有第二类型的掺杂剂的第一区域，并且第一区域与周围衬底形成第一pn结。 至少第一阱区形成在衬底中并且掺杂有第二类型的掺杂剂以与衬底形成第二pn结。 第一阱区经由半导体开关电连接到垂直晶体管的第一区域。 半导体器件包括检测电路，其集成在衬底中并被配置为检测第一pn结是否被反向偏置。 当第一个pn-junction反向偏置时，开关打开，并且当第一个pn结不被反向偏置时开关闭合。

公开(公告)号：US09070765B2

公开(公告)日：2015-06-30

申请号：US13760200

申请日：2013-02-06

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Andrew Wood

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/7823 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7816

Abstract: A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region.

Abstract translation: 半导体器件包括第一导电类型的半导体材料的外延层，从外延层的主表面延伸到外延层中的第二（相对）导电类型的体区，设置第一导电类型的源极区域 以及沿着主表面从源区域沿主体区域横向延伸的通道区域。 第二导电类型的电荷补偿区域可以在主体区域下方设置，该主体区域在与主表面平行的方向上延伸，并且在主表面处的源极和主体区域之间的pn结之前终止，和/或附加 具有至少一个峰值掺杂浓度的第一导电类型的区域，其中每个峰值掺杂浓度在主表面的外延层中比器件沟道区的峰值掺杂浓度更深。

公开(公告)号：US12021139B2

公开(公告)日：2024-06-25

申请号：US17121008

申请日：2020-12-14

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Norbert Krischke ,  Mathias Racki

IPC: G01K7/01 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/7803 ,  G01K7/01 ,  H01L27/0623 ,  H01L29/66272 ,  H01L29/7304 ,  H01L29/732

Abstract: A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 MΩ.

公开(公告)号：US20210193827A1

公开(公告)日：2021-06-24

申请号：US17121008

申请日：2020-12-14

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Norbert Krischke ,  Mathias Racki

IPC: H01L29/78 ,  H01L29/732 ,  H01L29/73 ,  H01L27/06 ,  H01L29/66 ,  G01K7/01

Abstract: A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 MΩ.

公开(公告)号：US20190043982A1

公开(公告)日：2019-02-07

申请号：US16050950

申请日：2018-07-31

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Marius Aurel Bodea

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

Abstract: Disclosed are a transistor device and a method. The transistor device includes a semiconductor body with a first surface, an inner region, and an edge region, a drift region of a first doping type in the inner region and the edge region, a plurality of transistor cells in the inner region, and a termination structure in the edge region. The termination structure includes a recess extending from the first surface in the edge region into the semiconductor body, and a floating compensation region with dopant atoms of a second doping type complementary to the first doping type in the drift region adjacent the recess.

公开(公告)号：US10199490B2

公开(公告)日：2019-02-05

申请号：US15915890

申请日：2018-03-08

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Radu Eugen Cazimirovici ,  Dietmar Kotz ,  Thomas Ostermann

IPC: H01L29/78 ,  H01L27/08 ,  H01L21/82 ,  H01L21/263 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66

Abstract: A semiconductor device includes a guard structure located laterally between a first active area of a semiconductor substrate and a second active area of the semiconductor substrate. The guard structure includes a first doping region located at a front side surface of the semiconductor substrate, and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure. Corresponding methods for forming the semiconductor device are also described.

公开(公告)号：US20170373182A1

公开(公告)日：2017-12-28

申请号：US15627481

申请日：2017-06-20

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Dietmar Kotz ,  Radu Eugen Cazimirovici ,  Thomas Ostermann

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L21/263 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/263 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66712

Abstract: A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

公开(公告)号：US09590091B2

公开(公告)日：2017-03-07

申请号：US14466198

申请日：2014-08-22

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Paolo Del Croce ,  Luca Petruzzi ,  Norbert Krischke

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7811 ,  H01L21/765 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0688 ,  H01L29/7805

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract translation: 根据半导体器件的实施例，半导体器件在半导体衬底中包括良好的功率器件，在衬底中良好的逻辑器件，并且通过衬底的分离区与阱与阱的间隔开，并且少数载流子转换 在分离区域中包括第一导电类型的第一掺杂区域，在分离区域中具有第二导电类型的第二掺杂区域和连接第一和第二掺杂区域的导电层。 第二掺杂区域包括插入在第一掺杂区域和功率器件阱之间的第一部分和插入在第一掺杂区域和逻辑器件阱之间的第二部分。

公开(公告)号：US09344078B1

公开(公告)日：2016-05-17

申请号：US14602791

申请日：2015-01-22

Applicant: Infineon Technologies AG

Inventor： Adrian Finney ,  Bogdan-Eugen Matei

IPC: H01L21/332 ,  H03K17/082 ,  H01L27/02 ,  H01L29/78 ,  H01L27/06

CPC classification number: H03K17/0822 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/7802

Abstract: A monolithic integrated circuit includes a low-voltage control circuit, a vertical power transistor, and a source follower. The vertical power transistor includes at least a drain. The source follower includes a drain that is coupled to the drain of the vertical power transistor, a gate that is coupled to a limit voltage node, and a source that is coupled to a high impedance node. The source follower is arranged such that a source voltage at the source of the source follower is a voltage-limited version of the drain voltage of the vertical power transistor. The low-voltage control circuit includes a driver and protection circuit that is arranged to detect the source voltage, to drive the vertical power transistor, and to adjust how the vertical power transistor is biased based, at least in part, on the source voltage.

Abstract translation: 单片集成电路包括低压控制电路，垂直功率晶体管和源极跟随器。 垂直功率晶体管至少包括漏极。 源极跟随器包括耦合到垂直功率晶体管的漏极的漏极，耦合到极限电压节点的栅极和耦合到高阻抗节点的源极。 源极跟随器被布置成使得源极跟随器的源极处的源极电压是垂直功率晶体管的漏极电压的电压限制形式。 所述低压控制电路包括驱动器和保护电路，所述驱动器和保护电路被布置成至少部分地基于所述源极电压来检测所述源极电压，驱动所述垂直功率晶体管以及调整所述垂直功率晶体管的偏置方式。

公开(公告)号：US09159719B2

公开(公告)日：2015-10-13

申请号：US13951157

申请日：2013-07-25

Applicant: Infineon Technologies AG

Inventor： Michael Mayerhofer ,  Andrei Cobzaru ,  Adrian Finney ,  Ulrich Glaser ,  Gilles Guerrero ,  Bogdan-Eugen Matei ,  Markus Mergens

IPC: H02H9/00 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A two-stage protection device for an electronic component protects against transient disturbances. The electronic component may be a semiconductor component, and may include one or multiple transistors and/or an integrated circuit. The protection device is connected to at least a first contact and a second contact of the electronic component, and is disposed essentially in parallel to the component that is to be protected, between the first contact and the second contact. The protection device includes a first stage with at least one diode and a second stage separated from the first stage by a resistor. The second stage includes at least one diode arrangement having two back-to-back disposed diodes which are disposed cathode-to-cathode.

Abstract translation: 用于电子部件的两级保护装置可防止瞬态干扰。 电子部件可以是半导体部件，并且可以包括一个或多个晶体管和/或集成电路。 保护装置连接到电子部件的至少第一触点和第二触点，并且在第一触点和第二触点之间基本上与被保护部件平行地设置。 保护装置包括具有至少一个二极管的第一级和通过电阻与第一级分离的第二级。 第二级包括至少一个二极管布置，其具有阴极至阴极设置的两个背对背布置的二极管。