公开(公告)号：US20130099289A1

公开(公告)日：2013-04-25

申请号：US13711404

申请日：2012-12-11

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC: H01L23/52

CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。

公开(公告)号：US08502276B2

公开(公告)日：2013-08-06

申请号：US13711404

申请日：2012-12-11

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Nirschl ,  Michael Bollu ,  Wolf Allers

IPC: H01L23/52

CPC classification number: H01L23/52 ,  G11C5/063 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract translation: 本发明的实施例描述了紧凑型存储器阵列。 在一个实施例中，存储单元阵列包括设置在衬底上的第一，第二和第三栅极线，第二栅极线设置在第一和第三栅极线之间。 第一，第二和第三栅极线形成存储单元阵列的相邻栅极线。 存储单元阵列还包括布置在第一栅极线上的第一金属线，耦合到第一栅极线的第一金属线; 第二金属线设置在第二栅极线上，第二金属线耦合到第二栅极线; 以及设置在所述第三栅极线上的第三金属线，所述第三金属线耦合到所述第三栅极线。 第一金属线，第二金属线和第三金属线设置在不同的金属化水平。