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    CIRCUIT WITH LOAD JUMP MITIGATION
    3.
    发明申请
    CIRCUIT WITH LOAD JUMP MITIGATION 有权

    公开(公告)号：US20240385640A1

    公开(公告)日：2024-11-21

    申请号：US18318038

    申请日：2023-05-16

    Applicant: Infineon Technologies AG

    Inventor： Dyson Wilkes ,  Miqdad Haji ,  Mark Selby ,  Neil Stuart Hastie

    IPC: G06F1/08 ,  G06F1/28

    Abstract: A circuit having load jump mitigation, including: circuit processing stages arranged in a pipeline configuration and operable based on respective stage clock signals; and clock control circuits respectively connected to the circuit processing stages to control the respective stage clock signals. Each of the clock control circuits is operable to: enable the respective stage clock signal in response to receiving a data in signal representing that the respective circuit processing stage begins to receive valid data for processing; disable the respective stage clock signal based on a predetermined respective circuit processing stage processing delay having elapsed since the respective circuit processing stage received any valid data; and enable a next of the clock control circuits, which is connected to a next of the circuit processing stages, based on the predetermined respective circuit processing stage processing delay having elapsed since the respective stage clock signal was enabled, indicating that the respective circuit processing stage is beginning to send the processed valid data to the next circuit processing stage.

    Circuit with load jump mitigation
    5.
    发明授权
    Circuit with load jump mitigation 有权

    公开(公告)号：US12181912B2

    公开(公告)日：2024-12-31

    申请号：US18318038

    申请日：2023-05-16

    Applicant: Infineon Technologies AG

    Inventor： Dyson Wilkes ,  Miqdad Haji ,  Mark Selby ,  Neil Stuart Hastie

    IPC: G06F1/08 ,  G06F1/28

    Abstract: A circuit having load jump mitigation, including: circuit processing stages arranged in a pipeline configuration and operable based on respective stage clock signals; and clock control circuits respectively connected to the circuit processing stages to control the respective stage clock signals. Each of the clock control circuits is operable to: enable the respective stage clock signal in response to receiving a data in signal representing that the respective circuit processing stage begins to receive valid data for processing; disable the respective stage clock signal based on a predetermined respective circuit processing stage processing delay having elapsed since the respective circuit processing stage received any valid data; and enable a next of the clock control circuits, which is connected to a next of the circuit processing stages, based on the predetermined respective circuit processing stage processing delay having elapsed since the respective stage clock signal was enabled, indicating that the respective circuit processing stage is beginning to send the processed valid data to the next circuit processing stage.

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