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公开(公告)号:US11424932B2
公开(公告)日:2022-08-23
申请号:US16913043
申请日:2020-06-26
Applicant: Infineon Technologies AG
Inventor: Andreas Graefe , Laurent Heidt , Albrecht Mayer
Abstract: A communication device is described including a receiver configured to receive a message including message data and a message authentication code, a first register for storing a received message authentication code and a second register for storing a computed message authentication code. The device also includes a first processor configured to extract the message authentication code from the message and to store the message authentication code in the first register, a second processor configured to compute a message authentication code based on the message data and to store the computed message authentication code in the second register, and a comparing circuit configured to compare the contents of the first register and the second register and to provide a comparison result. The device includes access control circuitry configured to prevent access by the second processor to the first register and to allow access by the first processor to the first register and to prevent access by the first processor to the second register and to allow access by the second processor to the second register.
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公开(公告)号:US11301249B2
公开(公告)日:2022-04-12
申请号:US16678215
申请日:2019-11-08
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer , Neil Stuart Hastie , Pawel Jewstafjew
IPC: G06F9/30
Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.
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公开(公告)号:US10592395B2
公开(公告)日:2020-03-17
申请号:US15945027
申请日:2018-04-04
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer , Glenn Ashley Farrall
IPC: G06F9/30 , G06F11/36 , G06F9/35 , G05B19/042
Abstract: A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.
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公开(公告)号:US20180300219A1
公开(公告)日:2018-10-18
申请号:US15945027
申请日:2018-04-04
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer , Glenn Ashley Farrall
CPC classification number: G06F11/364 , G05B19/042 , G06F9/30076 , G06F9/35 , G06F11/3656
Abstract: A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.
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公开(公告)号:US10061729B2
公开(公告)日:2018-08-28
申请号:US15924934
申请日:2018-03-19
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer , Joerg Schepers , Frank Hellwig
CPC classification number: G06F13/364 , G06F13/24 , G06F13/404 , G06F13/4282 , G06F15/7807
Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.
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公开(公告)号:US20180011776A1
公开(公告)日:2018-01-11
申请号:US15712536
申请日:2017-09-22
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer
CPC classification number: G06F11/3636 , G06F11/3466 , G06F11/3476 , G06F2201/865
Abstract: An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit.
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公开(公告)号:US20160080375A1
公开(公告)日:2016-03-17
申请号:US14483645
申请日:2014-09-11
Applicant: Infineon Technologies AG
Inventor: Laurent Heidt , Albrecht Mayer
IPC: H04L29/06
CPC classification number: H04L63/0876 , G06F2201/83 , H04L63/0823 , H04L63/123
Abstract: A method for processing data is suggested, and includes (i) conveying input data from a safety component to a security component, and (ii) calculating, at the security component, a second identifier based on the input data. The method further includes (iii) conveying the second identifier to the safety component, and (iv) verifying, at the safety component, a first identifier based on the second identifier.
Abstract translation: 提出了一种用于处理数据的方法,并且包括(i)将输入数据从安全组件传送到安全组件,以及(ii)在安全组件处基于输入数据计算第二标识符。 该方法还包括(iii)将第二标识符传送到安全部件,以及(iv)在安全部件处,基于第二标识符来验证第一标识符。
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公开(公告)号:US09092560B2
公开(公告)日:2015-07-28
申请号:US13632529
申请日:2012-10-01
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer
CPC classification number: G06F11/3476
Abstract: A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB.
Abstract translation: 用于并行地对多个CPU进行基于跟踪的测量的方法包括:接收信号以执行CPU并行跟踪模式,并使并行跟踪模式多路复用器将表示对本地存储器的所有数据写入的所有跟踪数据输出到单个 观察单位。 在一个实施例中,单个观察单元是处理器观察块(POB),在另一个实施例中是总线观察块(BOB)。 如果单个观察单元是BOB,则并行跟踪模式多路复用器首先通过BOB适配层路由本地存储器数据跟踪,以将CPU跟踪输出数据转换为由BOB理解的数据。
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公开(公告)号:US20140164848A1
公开(公告)日:2014-06-12
申请号:US13898065
申请日:2013-05-20
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer
IPC: G06F11/36
CPC classification number: G06F11/3636
Abstract: A system for tracing instruction pointers and data accesses in a plurality of processor cores includes a plurality of trace units. The plurality of trace units include at least one first trace unit configured to perform an instruction pointer trace and at least one second trace unit configured to perform a data trace. The system includes a multiplexer coupled between the plurality of processor cores and the plurality of trace units. The multiplexer is configured to selectively connect one trace unit of the plurality of trace units to one processor core of the plurality of processor cores. The multiplexer is configured during run time based on one of hardware triggers and software.
Abstract translation: 用于在多个处理器核心中跟踪指令指针和数据访问的系统包括多个跟踪单元。 多个跟踪单元包括被配置为执行指令指针跟踪的至少一个第一跟踪单元和被配置为执行数据跟踪的至少一个第二跟踪单元。 该系统包括耦合在多个处理器核心和多个跟踪单元之间的多路复用器。 多路复用器被配置为选择性地将多个跟踪单元的跟踪单元连接到多个处理器核心中的一个处理器核心。 多路复用器根据硬件触发器和软件之一在运行时配置。
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公开(公告)号:US12034256B2
公开(公告)日:2024-07-09
申请号:US17329559
申请日:2021-05-25
Applicant: Infineon Technologies AG
Inventor: Albrecht Mayer , Patrik Eder
CPC classification number: H01R13/665 , G06F13/4081
Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.
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