公开(公告)号：US20190181120A1

公开(公告)日：2019-06-13

申请号：US16213478

申请日：2018-12-07

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  April Coleen Tuazon Bernardez ,  Junny Abdul Wahid ,  Roslie Saini bin Bakar ,  Kon Hoe Chin ,  Hock Heng Chong ,  Kok Yau Chua ,  Hsieh Ting Kuek ,  Chee Hong Lee ,  Soon Lee Liew ,  Nurfarena Othman ,  Pei Luan Pok ,  Werner Reiss ,  Stefan Schmalzl

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/10

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

公开(公告)号：US10777536B2

公开(公告)日：2020-09-15

申请号：US16213478

申请日：2018-12-07

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  April Coleen Tuazon Bernardez ,  Junny Abdul Wahid ,  Roslie Saini bin Bakar ,  Kon Hoe Chin ,  Hock Heng Chong ,  Kok Yau Chua ,  Hsieh Ting Kuek ,  Chee Hong Lee ,  Soon Lee Liew ,  Nurfarena Othman ,  Pei Luan Pok ,  Werner Reiss ,  Stefan Schmalzl

IPC: H01L25/075 ,  H01L25/065 ,  H01L23/498 ,  B81B7/00 ,  H01L23/31 ,  B81C1/00 ,  H01L23/10

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.