公开(公告)号：US10777536B2

公开(公告)日：2020-09-15

申请号：US16213478

申请日：2018-12-07

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  April Coleen Tuazon Bernardez ,  Junny Abdul Wahid ,  Roslie Saini bin Bakar ,  Kon Hoe Chin ,  Hock Heng Chong ,  Kok Yau Chua ,  Hsieh Ting Kuek ,  Chee Hong Lee ,  Soon Lee Liew ,  Nurfarena Othman ,  Pei Luan Pok ,  Werner Reiss ,  Stefan Schmalzl

IPC: H01L25/075 ,  H01L25/065 ,  H01L23/498 ,  B81B7/00 ,  H01L23/31 ,  B81C1/00 ,  H01L23/10

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.

公开(公告)号：US20240213035A1

公开(公告)日：2024-06-27

申请号：US18087377

申请日：2022-12-22

Applicant: Infineon Technologies AG

Inventor： Chew Yeek Lau ,  Swee Kah Lee ,  Fong Mei Lum ,  Kon Hoe Chin

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49579 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/8181

Abstract: A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

公开(公告)号：US20190181120A1

公开(公告)日：2019-06-13

申请号：US16213478

申请日：2018-12-07

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  April Coleen Tuazon Bernardez ,  Junny Abdul Wahid ,  Roslie Saini bin Bakar ,  Kon Hoe Chin ,  Hock Heng Chong ,  Kok Yau Chua ,  Hsieh Ting Kuek ,  Chee Hong Lee ,  Soon Lee Liew ,  Nurfarena Othman ,  Pei Luan Pok ,  Werner Reiss ,  Stefan Schmalzl

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/10

Abstract: Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.