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公开(公告)号：US20230244820A1
公开(公告)日：2023-08-03
申请号：US18153578
申请日：2023-01-12
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , Joel Hatsch , Artur Wroblewski
IPC: G06F21/75 , H03K19/003 , H03K3/037 , G06F21/72
CPC classification number: G06F21/75 , H03K19/003 , H03K3/037 , G06F21/72
Abstract: A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line. The logic path and the clock signal line are formed such that their delays are such that, depending on a value of the secret bit, a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal.
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公开(公告)号：US20220293852A1
公开(公告)日：2022-09-15
申请号：US17689604
申请日：2022-03-08
Applicant: Infineon Technologies AG
Inventor： Artur Wroblewski , Joel Hatsch , Christoph Saas , Stefan Seidl
Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.
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公开(公告)号：US20250028892A1
公开(公告)日：2025-01-23
申请号：US18779386
申请日：2024-07-22
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl
IPC: G06F30/39
Abstract: Physically obfuscated circuit including subcircuits each having: series-connected transistors of a first conductivity; a transistor of a second conductivity; wherein the transistors are connected such that the series-connected transistors, if supplied with a first reference potential at their respective control terminal, deliver a second reference potential different from the first reference potential to the control terminal of the transistor of the second conductivity; and the transistor of the second conductivity, if supplied with a second reference potential at its control terminal, delivers the first reference potential to the control terminal of each of the series-connected transistors; and a precharge circuit to precharge the subcircuit to a first state in which the potential at the control terminal of the transistor of the second conductivity is different from the second reference potential and the potential at the control terminal of each of the series-connected transistors is different from the first reference potential.
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公开(公告)号：US10749338B2
公开(公告)日：2020-08-18
申请号：US15902216
申请日：2018-02-22
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , David Alvarez
Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.
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Patent Agency Ranking
公开(公告)号：US12182316B2
公开(公告)日：2024-12-31
申请号：US18153578
申请日：2023-01-12
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , Joel Hatsch , Artur Wroblewski
IPC: G06F21/75 , G06F21/72 , H03K3/037 , H03K19/003
Abstract: A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line. The logic path and the clock signal line are formed such that their delays are such that, depending on a value of the secret bit, a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by the second clocked memory element with the same clock edge of the clock signal, or a logic level change of the first clocked memory element with a clock edge of a clock signal on the clock signal line affects a logic level output by second clocked memory element with any clock edge coming after the next clock edge of the clock signal.
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公开(公告)号：US20240372736A1
公开(公告)日：2024-11-07
申请号：US18650742
申请日：2024-04-30
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , Berndt Gammel
Abstract: A method for evaluating a trustworthiness of sets of a physically unclonable function (PUF) elements, includes: obtaining first information related to a condition of a first set of PUF elements; obtaining second information related to a condition of a second set of PUF elements; and comparing the first information and the second information to determine the trustworthiness of at least one of the sets. The first set includes a first plurality of PUF elements and the second set includes a second plurality of PUF elements. The information related to the condition includes information indicating a respective subset of the set of PUF elements being used or unused when utilizing the respective set of the PUF elements, and/or includes respective error correction information for a bit sequence generated when utilizing the respective set of the PUF.
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公开(公告)号：US12232433B2
公开(公告)日：2025-02-18
申请号：US17689604
申请日：2022-03-08
Applicant: Infineon Technologies AG
Inventor： Artur Wroblewski , Joel Hatsch , Christoph Saas , Stefan Seidl
Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.
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8.发明公开公开(公告)号：US20230153472A1
公开(公告)日：2023-05-18
申请号：US17983839
申请日：2022-11-09
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , Joel Hatsch , Artur Wroblewski
IPC: G06F21/75
CPC classification number: G06F21/755
Abstract: A bit generation circuit having a plurality of signal chains, where for each chain, a first input of an input multiplexer is connected to another of the signal chains and the multiplexer is configured so that, if a control signal indicating a normal operating mode is fed to the multiplexer, the multiplexer connects the first input to the path input of the signal chain. The second input of each multiplexer is connected to the output of a bit generation trigger circuit and, for each signal chain, the multiplexer is configured so that, if a control signal indicating a secret generation mode is fed to the multiplexer, it connects the second input to the path input of the signal chain. The bit generation circuit furthermore comprises an arbiter circuit connected to the path outputs of at least two signal chains and configured to output a secret bit depending on their states.
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公开(公告)号：US20190260203A1
公开(公告)日：2019-08-22
申请号：US15902216
申请日：2018-02-22
Applicant: Infineon Technologies AG
Inventor： Stefan Seidl , David Alvarez
Abstract: Techniques for electrostatic discharge (ESD) protection that apply a negative voltage to an MOS power clamp during an ESD event. The power clamp may be initially turned on by a short positive pulse to the gate to trigger the power clamp to switch into a parasitic bipolar mode, to quickly shunt the electrical energy from the ESD event around other circuitry. However, repeatedly triggering an NMOS power clamp into bipolar mode may cause the power clamp performance to degrade. For example, the NMOS power clamp may develop an increase in leakage current. The techniques of this disclosure apply a negative voltage to the gate of the power clamp which may reduce the holding and triggering voltage during the ESD event as well as improve leakage degradation of the power clamp after repeated ESD events.
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