公开(公告)号：US20240363700A1

公开(公告)日：2024-10-31

申请号：US18140782

申请日：2023-04-28

Applicant: Infineon Technologies AG

Inventor： Lars Mueller-Meskamp ,  Ralf Rudolf ,  Anton Mauder ,  Annett Winzer ,  Dirk Priefert ,  Christian Schippel ,  Thomas Kuenzig

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/404 ,  H01L29/7816

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 μm to 200 μm between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

公开(公告)号：US20230010004A1

公开(公告)日：2023-01-12

申请号：US17859453

申请日：2022-07-07

Applicant: Infineon Technologies AG

Inventor： Frank Dieter Pfirsch ,  Thomas Kuenzig

IPC: H01L29/40

Abstract: A power semiconductor device includes an active region and an edge termination region surrounding the active region. A field plate structure arranged around the active region includes at least one electrically conductive track electrically connected to a first potential of a first load terminal at a first joint and, at a second joint, electrically connected to a second potential of a second load terminal. The track forms at least n crossings, wherein n is greater 5, with a straight virtual line that extends from the active region towards an edge of the edge termination region. The difference in potential between adjacent two crossings increases in at least 50% of the length of the virtual line, and/or the difference in potential within, with respect to the active region, the first 20% of the length of virtual line is less than 10% of the total difference in potential along the virtual line.