公开(公告)号：US20170294299A1

公开(公告)日：2017-10-12

申请号：US15485232

申请日：2017-04-12

Applicant: Infineon Technologies AG

Inventor： Heiko Assmann ,  Felix Braun ,  Marcus Dankelmann ,  Stefan Doering ,  Karsten Friedrich ,  Udo Goetschkes ,  Andreas Greiner ,  Ralf Rudolf ,  Jens Schneider

IPC: H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L21/268

CPC classification number: H01L21/027 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02634 ,  H01L21/0271 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0607

Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.

公开(公告)号：US20240363700A1

公开(公告)日：2024-10-31

申请号：US18140782

申请日：2023-04-28

Applicant: Infineon Technologies AG

Inventor： Lars Mueller-Meskamp ,  Ralf Rudolf ,  Anton Mauder ,  Annett Winzer ,  Dirk Priefert ,  Christian Schippel ,  Thomas Kuenzig

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/404 ,  H01L29/7816

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 μm to 200 μm between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

公开(公告)号：US10546920B2

公开(公告)日：2020-01-28

申请号：US15902158

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Ralf Rudolf

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/74 ,  H01L21/761 ,  H01L29/10

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

公开(公告)号：US10468248B2

公开(公告)日：2019-11-05

申请号：US15485232

申请日：2017-04-12

Applicant: Infineon Technologies AG

Inventor： Heiko Aßmann ,  Felix Braun ,  Marcus Dankelmann ,  Stefan Doering ,  Karsten Friedrich ,  Udo Goetschkes ,  Andreas Greiner ,  Ralf Rudolf ,  Jens Schneider

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/027 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L29/06

Abstract: In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.

公开(公告)号：US20190312114A1

公开(公告)日：2019-10-10

申请号：US16376266

申请日：2019-04-05

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Ralf Rudolf

IPC: H01L29/40 ,  H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L21/765

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, such that a first section of a pn junction is formed between the semiconductor layer and the semiconductor substrate. A trench structure extends through the semiconductor layer into the semiconductor substrate. The trench structure includes an insulation structure and a contact structure. The insulation structure is formed between the semiconductor layer and the contact structure. The contact structure is electrically connected to the semiconductor substrate at a bottom of the trench. A first semiconductor region of the second conductivity type adjoins the insulation structure and extends along the trench structure into a depth range between the first section of the pn junction and the bottom, such that a second section of the pn junction is formed between the first semiconductor region and the semiconductor substrate.

公开(公告)号：US20180240868A1

公开(公告)日：2018-08-23

申请号：US15902158

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Ralf Rudolf

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/74 ,  H01L21/761 ,  H01L21/265

CPC classification number: H01L29/0623 ,  H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/1087

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.