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公开(公告)号：US20190123137A1
公开(公告)日：2019-04-25
申请号：US16216831
申请日：2018-12-11
IPC分类号： H01L29/06 , H01L21/265 , H01L21/324 , H01L21/225 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/66
摘要： A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.
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公开(公告)号：US10734480B2
公开(公告)日：2020-08-04
申请号：US15869737
申请日：2018-01-12
发明人： Maximilian Treiber , Franz Hirler
IPC分类号： H01L21/00 , H01L29/10 , H01L29/40 , H01L29/78 , H01L23/58 , H01L29/417 , H01L29/423 , H01L29/06 , H01L21/8234
摘要： A semiconductor device includes a transistor. The transistor includes a source region adjacent to a first main surface of a semiconductor substrate, the source region being electrically coupled to a source terminal via a source contact. The transistor further includes a gate electrode over the first main surface of the semiconductor substrate, a drain region adjacent to a second main surface of the semiconductor substrate, and a conductive plate vertically adjacent to the gate electrode. The conductive plate is in electrical contact with the source terminal. The transistor further includes an insulating material arranged between the conductive plate and the source contact in a direction parallel to the first main surface.
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公开(公告)号：US11189690B2
公开(公告)日：2021-11-30
申请号：US16715816
申请日：2019-12-16
发明人： Hans Weber , Ingo Muri , Maximilian Treiber , Daniel Tutuc
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/265
摘要： A method and a transistor device are disclosed. The method includes: forming first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and forming body regions and source regions of transistor cells in the inner region of the semiconductor body. Forming the first regions and second regions includes: forming semiconductor layers one on top of the other; and in each of the semiconductor layers and before forming a respective next one of the semiconductor layers, forming trenches in the inner region and the edge region and implanting dopant atoms into a first sidewall and a second sidewall of each trench. Implanting the dopant atoms into at least one of the semiconductor layers includes partly covering the trenches in the edge region during an implantation process.
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公开(公告)号：US10651271B2
公开(公告)日：2020-05-12
申请号：US16216831
申请日：2018-12-11
IPC分类号： H01L21/265 , H01L29/06 , H01L29/40 , H01L21/225 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/324
摘要： A method for forming a field-effect semiconductor device includes providing a wafer having a substantially compensated semiconductor layer extending to an upper side and including a semiconductor material which is co-doped with n-type dopants and p-type dopants. A peripheral area laterally surrounding an active area are defined in the wafer. Trenches in the active area are filled with a substantially intrinsic semiconductor material. More p-type dopants than n-type dopants are diffused from the compensated semiconductor layer into the intrinsic semiconductor material to form a plurality of p-type compensation regions in the trenches which are separated from each other by respective n-type drift portions. P-type dopants are introduced at least into a semiconductor zone of the peripheral area, so that the semiconductor zone and a dielectric layer on the upper side form an interface. A horizontal extension of the interface is larger than a vertical extension of the trenches.
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公开(公告)号：US10553681B2
公开(公告)日：2020-02-04
申请号：US16104465
申请日：2018-08-17
发明人： Hans Weber , Franz Hirler , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L29/06 , H01L29/15 , H01L29/66 , H01L21/225 , H01L29/10 , H01L21/265 , H01L21/266 , H01L29/78
摘要： A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.
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公开(公告)号：US20180204914A1
公开(公告)日：2018-07-19
申请号：US15869737
申请日：2018-01-12
发明人： Maximilian Treiber , Franz Hirler
IPC分类号： H01L29/10 , H01L29/423 , H01L29/417 , H01L23/58 , H01L21/8234
摘要： A semiconductor device includes a transistor. The transistor includes a source region adjacent to a first main surface of a semiconductor substrate, the source region being electrically coupled to a source terminal via a source contact. The transistor further includes a gate electrode over the first main surface of the semiconductor substrate, a drain region adjacent to a second main surface of the semiconductor substrate, and a conductive plate vertically adjacent to the gate electrode. The conductive plate is in electrical contact with the source terminal. The transistor further includes an insulating material arranged between the conductive plate and the source contact in a direction parallel to the first main surface.
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公开(公告)号：US11342187B2
公开(公告)日：2022-05-24
申请号：US16850309
申请日：2020-04-16
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08
摘要： Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
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公开(公告)号：US20190058038A1
公开(公告)日：2019-02-21
申请号：US16104465
申请日：2018-08-17
发明人： Hans Weber , Franz Hirler , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L29/06 , H01L29/15 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265 , H01L21/266 , H01L21/225
摘要： A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.
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公开(公告)号：US20190051529A1
公开(公告)日：2019-02-14
申请号：US16158974
申请日：2018-10-12
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/78 , H01L29/66 , H01L29/06
摘要： Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
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公开(公告)号：US10109489B2
公开(公告)日：2018-10-23
申请号：US15648987
申请日：2017-07-13
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/06 , H01L29/66 , H01L29/78
摘要： Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
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