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公开(公告)号：US20220029013A1
公开(公告)日：2022-01-27
申请号：US17494098
申请日：2021-10-05
IPC分类号： H01L29/78 , H01L29/40 , H01L21/324 , H01L29/66 , H01L21/265 , H01L29/08
摘要： A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm
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公开(公告)号：US11764296B2
公开(公告)日：2023-09-19
申请号：US17494098
申请日：2021-10-05
IPC分类号： H01L29/78 , H01L29/40 , H01L21/324 , H01L29/66 , H01L21/265 , H01L29/08 , H01L29/417 , H01L29/10
CPC分类号： H01L29/7813 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/086 , H01L29/407 , H01L29/66734 , H01L29/1095 , H01L29/41766
摘要： A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm
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公开(公告)号：US20190123193A1
公开(公告)日：2019-04-25
申请号：US16165831
申请日：2018-10-19
IPC分类号： H01L29/78 , H01L29/40 , H01L29/08 , H01L29/66 , H01L21/265 , H01L21/324
摘要： In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dpn from the first major surface, wherein 50 nm
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公开(公告)号：US20160155796A1
公开(公告)日：2016-06-02
申请号：US14942389
申请日：2015-11-16
IPC分类号： H01L29/06 , H01L29/739 , H01L29/08 , H01L29/861
CPC分类号： H01L29/0821 , H01L29/0619 , H01L29/0661 , H01L29/0834 , H01L29/1608 , H01L29/2003 , H01L29/452 , H01L29/456 , H01L29/7393 , H01L29/7397 , H01L29/861 , H01L29/8611
摘要： A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.
摘要翻译： 半导体器件包括在半导体本体的第一表面处的第一负载端子和在相对表面处的第二负载端子。 活动设备区域被边缘终止区域包围。 在边缘终端区域中不存在负载端子触点，并且在第一表面处与有源器件区域中的半导体主体电连接。 正温度系数结构在第一和第二负载端子中的至少一个与第一和第二表面中的相应一个之间。 在对于半导体器件规定的最大工作温度之上，正温度系数结构的电阻率在至多50K的温度范围内增加至少两个数量级。正温度系数结构的面积覆盖度为 在边缘终止区域比活动设备区域更大。
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公开(公告)号：US20200243340A1
公开(公告)日：2020-07-30
申请号：US16850309
申请日：2020-04-16
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/66 , H01L29/78 , H01L29/06
摘要： Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
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公开(公告)号：US10679855B2
公开(公告)日：2020-06-09
申请号：US16158974
申请日：2018-10-12
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08
摘要： Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
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公开(公告)号：US10461739B2
公开(公告)日：2019-10-29
申请号：US15921878
申请日：2018-03-15
发明人： Thomas Basler , Roman Baburske , Johannes Georg Laven , Franz-Josef Niedernostheide , Hans-Joachim Schulze
IPC分类号： H03K17/567 , H03K17/12 , H03K17/687 , H01L27/06 , H01L29/78 , H02H3/08 , H01L29/739 , H03K17/08 , H03K17/082 , H01L27/088 , H01L27/07
摘要： Transistor devices are provided. A transistor device includes a unipolar transistor coupled between a first terminal and a second terminal; and a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal. The bipolar transistor is configured to carry a majority of a current flowing through the transistor device when at least one of the current or a control voltage controlling the unipolar transistor and the bipolar transistor exceeds a predetermined threshold. The bipolar transistor is further configured to have a threshold voltage higher than a threshold voltage of the unipolar transistor, and a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V.
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公开(公告)号：US20180019132A1
公开(公告)日：2018-01-18
申请号：US15648987
申请日：2017-07-13
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/0634 , H01L29/0696 , H01L29/66712 , H01L29/7813
摘要： Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.
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公开(公告)号：US09660029B2
公开(公告)日：2017-05-23
申请号：US14942389
申请日：2015-11-16
IPC分类号： H01L29/66 , H01L29/08 , H01L29/861 , H01L29/739 , H01L29/45 , H01L29/06 , H01L29/16 , H01L29/20
CPC分类号： H01L29/0821 , H01L29/0619 , H01L29/0661 , H01L29/0834 , H01L29/1608 , H01L29/2003 , H01L29/452 , H01L29/456 , H01L29/7393 , H01L29/7397 , H01L29/861 , H01L29/8611
摘要： A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.
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公开(公告)号：US11342187B2
公开(公告)日：2022-05-24
申请号：US16850309
申请日：2020-04-16
发明人： Anton Mauder , Hans Weber , Franz Hirler , Johannes Georg Laven , Hans-Joachim Schulze , Werner Schustereder , Maximilian Treiber , Daniel Tutuc , Andreas Voerckel
IPC分类号： H01L21/265 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08
摘要： Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.
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