-
公开(公告)号：US10742327B2
公开(公告)日：2020-08-11
申请号：US16600328
申请日：2019-10-11
Applicant: INPHI CORPORATION
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Paul Voois , Ramiro Rogelio Lopez , Jorge Manuel Finochietto , Norman L. Swenson , Mario Rafael Hueda , Hugo Santiago Carrer , Vadim Gutnik , Adrián Ulises Morales , Martin Ignacio Del Barco , Martin Carlos Asinari , Federico Nicolas Paredes , Alfredo Javier Taddei , Mauro Marcelo Bruni , Damian Alfonso Morero , Facundo Abel Alcides Ramos , María Laura Ferster , Elvio Adrian Serrano , Pablo Gustavo Quiroga , Roman Antonio Arenas , Matias German Schnidrig , Alejandro Javier Schwoykoski
IPC: H04B10/40 , H04B10/516 , H04B10/61 , H04L7/00
Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
-
2.发明授权公开(公告)号：US10763972B2
公开(公告)日：2020-09-01
申请号：US16694391
申请日：2019-11-25
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro Marcelo Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
-
3.发明授权公开(公告)号：US09876583B2
公开(公告)日：2018-01-23
申请号：US15623292
申请日：2017-06-14
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro M. Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
CPC classification number: H04B10/6162 , H04B10/616 , H04B10/6165 , H04L7/0075 , H04L7/0079
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
-
Patent Agency Ranking
4.发明授权公开(公告)号：US10530493B2
公开(公告)日：2020-01-07
申请号：US16212461
申请日：2018-12-06
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro Marcelo Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
-
公开(公告)号：US10177851B2
公开(公告)日：2019-01-08
申请号：US15647765
申请日：2017-07-12
Applicant: INPHI CORPORATION
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Paul Voois , Ramiro Rogelio Lopez , Jorge Manuel Finochietto , Norman L. Swenson , Mario Rafael Hueda , Hugo Santiago Carrer , Vadim Gutnik , Adrián Ulises Morales , Martin Ignacio Del Barco , Martin Carlos Asinari , Federico Nicolas Paredes , Alfredo Javier Taddei , Mauro Marcelo Bruni , Damian Alfonso Morero , Facundo Abel Alcides Ramos , María Laura Ferster , Elvio Adrian Serrano , Pablo Gustavo Quiroga , Roman Antonio Arenas , Matias German Schnidrig , Alejandro Javier Schwoykoski
IPC: H04B10/00 , H04B10/516 , H04B10/40 , H04B10/61 , H04L7/00
Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
-
6.发明授权公开(公告)号：US09712253B1
公开(公告)日：2017-07-18
申请号：US14869676
申请日：2015-09-29
Applicant: Inphi Corporation
Inventor： Mario Rafael Hueda , Mauro M. Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
CPC classification number: H04B10/6162 , H04B10/616 , H04B10/6165 , H04L7/0075 , H04L7/0079
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
-
7.发明授权公开(公告)号：US10181908B2
公开(公告)日：2019-01-15
申请号：US15839698
申请日：2017-12-12
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro Marcelo Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
-
公开(公告)号：US09735881B1
公开(公告)日：2017-08-15
申请号：US15148645
申请日：2016-05-06
Applicant: Inphi Corporation
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Paul Voois , Ramiro Rogelio Lopez , Jorge Manuel Finochietto , Norman L. Swenson , Mario Rafael Hueda , Hugo Santiago Carrer , Vadim Gutnik , Adrián Ulises Morales , Martin Ignacio del Barco , Martin Carlos Asinari , Federico Nicolas Paredes , Alfredo Javier Taddei , Mauro M. Bruni , Damian Alfonso Morero , Facundo Abel Alcides Ramos , María Laura Ferster , Elvio Adrian Serrano , Pablo Gustavo Quiroga , Roman Antonio Arenas , Matias German Schnidrig , Alejandro Javier Schwoykoski
IPC: H04B10/00 , H04B10/516 , H04L7/00
CPC classification number: H04B10/516 , H04B10/40 , H04B10/61 , H04L7/0075
Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.018 seconds)
