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公开(公告)号：US11005571B2
公开(公告)日：2021-05-11
申请号：US16892146
申请日：2020-06-03
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , José L. Correa Lust , Damian Alfonso Morero
IPC: H04B10/61 , H04L27/227 , H04L27/38 , H04B10/40 , H04J14/02
Abstract: A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.
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公开(公告)号：US10958354B2
公开(公告)日：2021-03-23
申请号：US16703637
申请日：2019-12-04
Applicant: INPHI CORPORATION
Inventor： Damián Alfonso Morero , Mario Rafael Hueda , Oscar Ernesto Agazzi
Abstract: A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.
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公开(公告)号：US10742327B2
公开(公告)日：2020-08-11
申请号：US16600328
申请日：2019-10-11
Applicant: INPHI CORPORATION
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Paul Voois , Ramiro Rogelio Lopez , Jorge Manuel Finochietto , Norman L. Swenson , Mario Rafael Hueda , Hugo Santiago Carrer , Vadim Gutnik , Adrián Ulises Morales , Martin Ignacio Del Barco , Martin Carlos Asinari , Federico Nicolas Paredes , Alfredo Javier Taddei , Mauro Marcelo Bruni , Damian Alfonso Morero , Facundo Abel Alcides Ramos , María Laura Ferster , Elvio Adrian Serrano , Pablo Gustavo Quiroga , Roman Antonio Arenas , Matias German Schnidrig , Alejandro Javier Schwoykoski
IPC: H04B10/40 , H04B10/516 , H04B10/61 , H04L7/00
Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.
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公开(公告)号：US10027423B1
公开(公告)日：2018-07-17
申请号：US15187711
申请日：2016-06-20
Applicant: Inphi Corporation
Inventor： Damián Alfonso Morero , Martin Carlos Asinari , Martin Ignacio del Barco , Mario Rafael Hueda , Lucas Javier Yoaquino
Abstract: An adaptive demapper adaptively demaps an input symbol. An input symbol is received and demapped in a hard-output demapper to generate a current detected symbol corresponding to a constellation point on a current constellation closest to the input symbol. A corrected inverse of a current noise power estimate is determined by updating a previous noise power estimate based on a difference between the input symbol and the current detected symbol. In a soft-output demapper, a log likelihood ratio corresponding to the current detected symbol is determined based on the corrected inverse of the current noise power estimate. The constellation point in the current constellation corresponding to the current detected symbol is then updated to generate an updated constellation based on a difference between the constellation point and the received input symbol.
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公开(公告)号：US09806823B2
公开(公告)日：2017-10-31
申请号：US15351173
申请日：2016-11-14
Applicant: Inphi Corporation
CPC classification number: H04B10/6165 , H04B10/616 , H04L1/0045 , H04L1/0054 , H04L7/033
Abstract: A receiver architecture and method recovers data received over an optical fiber channel in the presence of cycle slips. In a first cycle slip recovery architecture, a receiver detects and corrects cycle slips based on pilot symbols inserted in the transmitted data. In a second cycle slip recovery architecture, a coarse cycle slip detection is performed based on pilot symbols and a cycle slip position estimation is then performed based on carrier phase noise. The receiver compensates for cycle slips based on the position estimation.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10763972B2
公开(公告)日：2020-09-01
申请号：US16694391
申请日：2019-11-25
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro Marcelo Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
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公开(公告)号：US10103751B2
公开(公告)日：2018-10-16
申请号：US15188957
申请日：2016-06-21
Applicant: Inphi Corporation
Inventor： Damian Alfonso Morero , Mario Alejandro Castrillon , Matias German Schnidrig , Mario Rafael Hueda , Franco Paludi
Abstract: A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.
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公开(公告)号：US10097273B2
公开(公告)日：2018-10-09
申请号：US15839380
申请日：2017-12-12
Applicant: INPHI CORPORATION
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , German Cesar Augusto Luna , Carl Grace
IPC: H04B1/38 , H04L5/16 , H04B10/50 , H04B7/005 , H04L25/02 , H04B3/23 , H03M13/41 , H04B10/2507 , H04B10/294 , H04B10/69 , H04B1/04 , H04B10/40 , H04B7/0456
Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
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公开(公告)号：US10056981B2
公开(公告)日：2018-08-21
申请号：US15921496
申请日：2018-03-14
Applicant: INPHI CORPORATION
Inventor： Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , Martin Ignacio Del Barco , Pablo Gianni , Ariel Pola , Elvio Adrian Serrano , Alfredo Javier Taddei , Mario Alejandro Castrillon , Martin Serra , Ramiro Matteoda
CPC classification number: H04B10/6161 , H04B10/616 , H04L7/0075 , H04L27/01
Abstract: A receiver for fiber optic communications.
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10.发明授权公开(公告)号：US09876583B2
公开(公告)日：2018-01-23
申请号：US15623292
申请日：2017-06-14
Applicant: INPHI CORPORATION
Inventor： Mario Rafael Hueda , Mauro M. Bruni , Federico Nicolas Paredes , Hugo Santiago Carrer , Diego Ernesto Crivelli , Oscar Ernesto Agazzi , Norman L. Swenson , Seyedmohammadreza Motaghiannezam
CPC classification number: H04B10/6162 , H04B10/616 , H04B10/6165 , H04L7/0075 , H04L7/0079
Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
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