公开(公告)号：US10742327B2

公开(公告)日：2020-08-11

申请号：US16600328

申请日：2019-10-11

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Paul Voois ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Norman L. Swenson ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Vadim Gutnik ,  Adrián Ulises Morales ,  Martin Ignacio Del Barco ,  Martin Carlos Asinari ,  Federico Nicolas Paredes ,  Alfredo Javier Taddei ,  Mauro Marcelo Bruni ,  Damian Alfonso Morero ,  Facundo Abel Alcides Ramos ,  María Laura Ferster ,  Elvio Adrian Serrano ,  Pablo Gustavo Quiroga ,  Roman Antonio Arenas ,  Matias German Schnidrig ,  Alejandro Javier Schwoykoski

IPC: H04B10/40 ,  H04B10/516 ,  H04B10/61 ,  H04L7/00

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US09838131B1

公开(公告)日：2017-12-05

申请号：US14743660

申请日：2015-06-18

Applicant: Inphi Corporation

Inventor： Paul Voois ,  Diego Ernesto Crivelli ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Oscar Ernesto Agazzi ,  Nariman Yousefi ,  Norman L. Swenson

IPC: H04B10/04 ,  H04B10/00 ,  H04B10/12 ,  H04B10/40 ,  H04B10/58 ,  H04B10/2507

CPC classification number: H04B10/40 ,  H04B10/2507 ,  H04B10/58

Abstract: An optical communication system provides coherent optical transmission for metro applications. Relative to conventional solutions, the optical communication system can be implemented with reduced cost and can operate with reduced power consumption, while maintaining high data rate performance (e.g., 100 G). Furthermore, a programmable transceiver enables compatibility with a range of different types of optical networks having varying performance and power tradeoffs. In one embodiment, the optical communication system uses 100 Gb/s dual-polarization 16-point quadrature amplitude modulation (DP-16QAM) with non-linear pre-compensation of Indium Phosphide (InP) optics for low power consumption.

公开(公告)号：US10038506B2

公开(公告)日：2018-07-31

申请号：US15800745

申请日：2017-11-01

Applicant: INPHI CORPORATION

Inventor： Diego Ernesto Crivelli ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Jeffrey Zachan ,  Vadim Gutnik ,  Martin Ignacio Del Barco ,  Ramiro Rogelio Lopez ,  Shih Cheng Wang ,  Geoffrey O. Hatcher ,  Jorge Manuel Finochietto ,  Michael Yeo ,  Andre Chartrand ,  Norman L. Swenson ,  Paul Voois ,  Oscar Ernesto Agazzi

IPC: H04B10/00 ,  H04B10/61 ,  H04B10/40 ,  H04B10/2569 ,  H04J14/00

CPC classification number: H04B10/6162 ,  H04B10/2569 ,  H04B10/40 ,  H04B10/6161

Abstract: A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.

公开(公告)号：US09838140B1

公开(公告)日：2017-12-05

申请号：US15597120

申请日：2017-05-16

Applicant: Inphi Corporation

Inventor： Diego Ernesto Crivelli ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Jeffrey Zachan ,  Vadim Gutnik ,  Martin Ignacio del Barco ,  Ramiro Rogelio Lopez ,  Shih Cheng Wang ,  Geoffrey O. Hatcher ,  Jorge Manuel Finochietto ,  Michael Yeo ,  Andre Chartrand ,  Norman L. Swenson ,  Paul Voois ,  Oscar Ernesto Agazzi

IPC: H04B10/00 ,  H04B10/61 ,  H04B10/2569 ,  H04B10/40 ,  H04J14/00

CPC classification number: H04B10/6162 ,  H04B10/2569 ,  H04B10/40 ,  H04B10/6161

Abstract: A transceiver for fiber optic communications.

公开(公告)号：US10181908B2

公开(公告)日：2019-01-15

申请号：US15839698

申请日：2017-12-12

Applicant: INPHI CORPORATION

Inventor： Mario Rafael Hueda ,  Mauro Marcelo Bruni ,  Federico Nicolas Paredes ,  Hugo Santiago Carrer ,  Diego Ernesto Crivelli ,  Oscar Ernesto Agazzi ,  Norman L. Swenson ,  Seyedmohammadreza Motaghiannezam

IPC: H04B10/00 ,  H04B10/61 ,  H04L7/00

Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

公开(公告)号：US10069571B2

公开(公告)日：2018-09-04

申请号：US15797898

申请日：2017-10-30

Applicant: INPHI CORPORATION

Inventor： Paul Voois ,  Diego Ernesto Crivelli ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Oscar Ernesto Agazzi ,  Nariman Yousefi ,  Norman L. Swenson

IPC: H04B10/04 ,  H04B10/00 ,  H04B10/12 ,  H04B10/40 ,  H04B10/2507 ,  H04B10/58

Abstract: Methods of operating an optical communication system in coherent optical transmissions for metro applications. Relative to conventional solutions, the optical communication system can be implemented with reduced cost and can operate with reduced power consumption, while maintaining high data rate performance (e.g., 100 G). Furthermore, a programmable transceiver enables compatibility with a range of different types of optical networks having varying performance and power tradeoffs. In one embodiment, the optical communication system uses 100 Gb/s dual-polarization 16-point quadrature amplitude modulation (DP-16QAM) with non-linear pre-compensation of Indium Phosphide (InP) optics for low power consumption.

公开(公告)号：US09960855B2

公开(公告)日：2018-05-01

申请号：US15786108

申请日：2017-10-17

Applicant: INPHI CORPORATION

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Hugo Santiago Carrer ,  Mario Rafael Hueda ,  Martin Ignacio Del Barco ,  Pablo Gianni ,  Ariel Pola ,  Elvio Adrian Serrano ,  Alfredo Javier Taddei ,  Mario Alejandro Castrillon ,  Martin Serra ,  Ramiro Matteoda

IPC: H04B10/00 ,  H04B10/61 ,  H04L27/01 ,  H04L7/00 ,  H04J14/00

CPC classification number: H04B10/6161 ,  H04B10/616 ,  H04L7/0075 ,  H04L27/01

Abstract: A receiver for fiber optic communications.

公开(公告)号：US09882648B2

公开(公告)日：2018-01-30

申请号：US15387246

申请日：2016-12-21

Applicant: INPHI Corporation

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Hugo Santiago Carrer ,  Mario Rafael Hueda ,  German Cesar Augusto Luna ,  Carl Grace

IPC: H04B1/38 ,  H04L5/16 ,  H04B10/50 ,  H04B10/69 ,  H03M13/41 ,  H04L25/02 ,  H04B10/2507 ,  H04B10/294 ,  H04B3/23 ,  H04B7/005 ,  H04B1/04

CPC classification number: H04B10/5059 ,  H03M13/41 ,  H04B1/38 ,  H04B3/235 ,  H04B7/005 ,  H04B7/0456 ,  H04B10/25073 ,  H04B10/2941 ,  H04B10/40 ,  H04B10/6971 ,  H04B2001/0441 ,  H04B2201/709772 ,  H04L5/16 ,  H04L25/0202 ,  H04L25/025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

公开(公告)号：US09735881B1

公开(公告)日：2017-08-15

申请号：US15148645

申请日：2016-05-06

Applicant: Inphi Corporation

Inventor： Oscar Ernesto Agazzi ,  Diego Ernesto Crivelli ,  Paul Voois ,  Ramiro Rogelio Lopez ,  Jorge Manuel Finochietto ,  Norman L. Swenson ,  Mario Rafael Hueda ,  Hugo Santiago Carrer ,  Vadim Gutnik ,  Adrián Ulises Morales ,  Martin Ignacio del Barco ,  Martin Carlos Asinari ,  Federico Nicolas Paredes ,  Alfredo Javier Taddei ,  Mauro M. Bruni ,  Damian Alfonso Morero ,  Facundo Abel Alcides Ramos ,  María Laura Ferster ,  Elvio Adrian Serrano ,  Pablo Gustavo Quiroga ,  Roman Antonio Arenas ,  Matias German Schnidrig ,  Alejandro Javier Schwoykoski

IPC: H04B10/00 ,  H04B10/516 ,  H04L7/00

CPC classification number: H04B10/516 ,  H04B10/40 ,  H04B10/61 ,  H04L7/0075

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

公开(公告)号：US10530493B2

公开(公告)日：2020-01-07

申请号：US16212461

申请日：2018-12-06

Applicant: INPHI CORPORATION

Inventor： Mario Rafael Hueda ,  Mauro Marcelo Bruni ,  Federico Nicolas Paredes ,  Hugo Santiago Carrer ,  Diego Ernesto Crivelli ,  Oscar Ernesto Agazzi ,  Norman L. Swenson ,  Seyedmohammadreza Motaghiannezam

IPC: H04B10/61 ,  H04L7/00

Abstract: A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.