公开(公告)号：US09236871B1

公开(公告)日：2016-01-12

申请号：US14460653

申请日：2014-08-15

Applicant: Integrated Device Technology, Inc.

Inventor： Pengfei Hu ,  Brian Buell

IPC: H03L7/06 ,  H03L7/093 ,  H03M3/00

CPC classification number: H03L7/093 ,  H03L7/1974

Abstract: A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a second current carrying terminal electrically coupled to the input of the ADC. The impedance element can include a resistor and a capacitor, which are electrically connected in parallel. A gain device, such as a programmable multiplier, may also be provided, which has an input responsive to the signal generated at the output of the ADC and an output electrically coupled to the input of the DAC.

Abstract translation: 用于频率合成器（例如，PLL，UFT）的数字滤波器可以包括响应于其输入处的控制电压的模数（ADC）转换器和数模转换器 ，其具有响应于在ADC的输出处产生的信号的输入。 在DAC和ADC之间提供阻抗元件。 阻抗元件具有实际和无功分量，电耦合到DAC的输出的第一载流端子和电耦合到ADC的输入的第二载流端子。 阻抗元件可以包括并联电连接的电阻器和电容器。 还可以提供诸如可编程乘法器的增益器件，其具有响应于在ADC的输出处产生的信号的输入和电耦合到DAC的输入的输出。

公开(公告)号：US09838016B1

公开(公告)日：2017-12-05

申请号：US15050646

申请日：2016-02-23

Applicant: Integrated Device Technology, Inc.

Inventor： Pengfei Hu

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage signals developed at the first and second common-mode sensing terminals, respectively, and the reference signal generator is configured to provide the first and second drivers with a reference voltage having a magnitude that varies in response to changes in a signal generated at an output terminal of the comparator. This variation in the magnitude of the reference voltage supports a built-in adaptive response to changes in source-side termination in HCSL driver/receiver circuits.

公开(公告)号：US09118333B1

公开(公告)日：2015-08-25

申请号：US14013599

申请日：2013-08-29

Applicant: Integrated Device Technology, Inc.

Inventor： Benedykt Mika ,  Pengfei Hu

IPC: H03K21/00 ,  H03K23/00 ,  H03K23/70 ,  H03K23/68 ,  H03K23/66

CPC classification number: H03K23/70 ,  H03K21/00 ,  H03K21/023 ,  H03K21/38 ,  H03K23/00 ,  H03K23/667 ,  H03K23/68

Abstract: Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.

Abstract translation: 集成电路设备包括可以使用其中的多模式分频器（MMD）的可编程分频器，例如分数N分频器。 多模式分配器包括一个分级链div2 / 3单元，其被配置为支持链长控制操作，该操作排除在响应于链长度控制字节P 的值的变化期间产生中间除数 更新时间间隔，甚至可以完全关闭不参与除N运算的一个或多个div2 / 3单元，其中N是大于1的正整数。 div2 / 3单元被配置为包括模数输入端和模输出端，并且链长控制操作与提供给div2 / 3单元的模输入端的信号的幅度无关。