公开(公告)号：US20170212847A1

公开(公告)日：2017-07-27

申请号：US15480616

申请日：2017-04-06

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/12 ,  G06F13/40 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

公开(公告)号：US09905287B2

公开(公告)日：2018-02-27

申请号：US15480616

申请日：2017-04-06

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G11C11/4093 ,  G06F13/40 ,  G11C11/4076 ,  H04L25/02

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

公开(公告)号：US09653147B1

公开(公告)日：2017-05-16

申请号：US14956955

申请日：2015-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G11C11/4093 ,  G11C11/4076 ,  H04L25/02

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

公开(公告)号：US09583175B1

公开(公告)日：2017-02-28

申请号：US14956870

申请日：2015-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Praveen Rajan Singh ,  Yanbo Wang

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4096

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and (b) a combined resistive and capacitive load between the first and second differential write lines. The second circuit may be configured to (a) convert the first and the second differential write signals to a single-ended write signal and (b) present the single-ended write signal to the data bus.

Abstract translation: 一种装置包括第一电路和第二电路。 第一电路可以被配置为（a）缓冲在连接在存储器通道和存储器控制器之间的数据总线上呈现的写入信号，（b）在数据总线上呈现的缓冲器读取信号，以及（c）调节写入信号。 调节可以通过以下方式来实现：（i）将第二差分写入线上的写信号转换成第一差分写入线上的第一差分写入信号和第二差分写入线上的第二差分写入信号，以及（ii）连接（a）负阻抗和（ b）第一和第二差分写入线之间的组合的电阻和电容负载。 第二电路可以被配置为（a）将第一差分写入信号和第二差分写信号转换成单端写入信号，并且（b）将单端写入信号呈现给数据总线。

公开(公告)号：US20170162251A1

公开(公告)日：2017-06-08

申请号：US14956955

申请日：2015-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Yanbo Wang ,  Praveen Rajan Singh ,  Yue Yu ,  Craig DeSimone

IPC: G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/4068 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  H04L25/028 ,  H04L25/0286

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.