公开(公告)号：US10671300B1

公开(公告)日：2020-06-02

申请号：US16258972

申请日：2019-01-28

Applicant: Integrated Device Technology, Inc.

Inventor： Craig DeSimone ,  Praveen Singh ,  Alejandro Gonzalez ,  Yue Yu ,  YanBo Wang

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/4093

Abstract: A method for responding to a command sequence includes receiving a signal from a host carrying a plurality of commands in the command sequence, detecting a non-consecutive clock associated with a start of a current command in the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock.

公开(公告)号：US10198200B1

公开(公告)日：2019-02-05

申请号：US15367742

申请日：2016-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Craig DeSimone ,  Praveen Singh ,  Alejandro Gonzalez ,  Yue Yu ,  YanBo Wang

IPC: G06F3/06 ,  G11C11/4093 ,  G11C11/4096

Abstract: A method for responding to a command sequence includes receiving the command sequence associated with a targeted access to a memory system, detecting a non-consecutive clock associated with a start of the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock associated with the start of the command sequence.

公开(公告)号：US09860088B1

公开(公告)日：2018-01-02

申请号：US15367586

申请日：2016-12-02

Applicant: Integrated Device Technology, Inc.

Inventor： Craig DeSimone ,  Praveen Singh ,  Alejandro Gonzalez ,  Yue Yu ,  YanBo Wang

IPC: H04L25/03

CPC classification number: G11C11/4093 ,  G06F1/04 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4096 ,  H04L25/03057

Abstract: An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.