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公开(公告)号：US10911044B1
公开(公告)日：2021-02-02
申请号：US16704620
申请日：2019-12-05
发明人： Kyoung Chon Jin
IPC分类号： H03K17/68 , H03K17/687 , H03K3/037
摘要： An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal. The output circuit includes an output driver circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit, when activated, generates the output signal indicative of the second power supply voltage in response to a modified pull-up signal being the pull-up signal level-shifted to a third voltage range. The pull-down circuit, when activated, generates the output signal being the ground potential in response to the pull-down signal.
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公开(公告)号：US10984872B1
公开(公告)日：2021-04-20
申请号：US16704598
申请日：2019-12-05
发明人： Kyoung Chon Jin
摘要： A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.
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