公开(公告)号：US11895824B2

公开(公告)日：2024-02-06

申请号：US17667498

申请日：2022-02-08

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Gilbert Dewey ,  Abhishek A Sharma

IPC分类号： H10B12/00

CPC分类号： H10B12/36 ,  H10B12/056

摘要： A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.