公开(公告)号：US20240215267A1

公开(公告)日：2024-06-27

申请号：US18596623

申请日：2024-03-06

申请人： Monolithic 3D Inc.

发明人： Deepak C. Sekar ,  Zvi Or-Bach

IPC分类号： H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

摘要： A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

公开(公告)号：US11996411B2

公开(公告)日：2024-05-28

申请号：US16913796

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Anh Phan ,  Nicole K. Thomas ,  Urusa Alaan ,  Seung Hoon Sung ,  Christopher M. Neumann ,  Willy Rachmady ,  Patrick Morrow ,  Hui Jae Yoo ,  Richard E. Schenker ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ehren Mannebach

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H10B12/00

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H10B12/056

摘要： Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US11943912B2

公开(公告)日：2024-03-26

申请号：US17844111

申请日：2022-06-20

申请人： SK hynix Inc.

发明人： Dong-Soo Kim

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00 ,  H01L21/3105

CPC分类号： H10B12/34 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/32136 ,  H01L21/32155 ,  H01L21/76224 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785 ,  H10B12/053 ,  H10B12/056 ,  H10B12/36 ,  H01L21/31053 ,  H01L29/517

摘要： A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.

公开(公告)号：US11895824B2

公开(公告)日：2024-02-06

申请号：US17667498

申请日：2022-02-08

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Gilbert Dewey ,  Abhishek A Sharma

IPC分类号： H10B12/00

CPC分类号： H10B12/36 ,  H10B12/056

摘要： A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

公开(公告)号：US12112829B2

公开(公告)日：2024-10-08

申请号：US17575397

申请日：2022-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Ying Lee ,  Chia-En Huang ,  Meng-Sheng Chang

IPC分类号： G11C7/14 ,  G11C7/18 ,  H01L25/065 ,  H10B12/00

CPC分类号： G11C7/14 ,  G11C7/18 ,  H01L25/0655 ,  H10B12/056 ,  H10B12/36

摘要： A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

公开(公告)号：US20240222509A1

公开(公告)日：2024-07-04

申请号：US18608294

申请日：2024-03-18

申请人： Intel Corporation

发明人： Bernhard SELL

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H01L29/7853 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/7856 ,  H01L29/786 ,  H10B12/056 ,  H10B12/36 ,  H01L2924/13067

摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US11864376B2

公开(公告)日：2024-01-02

申请号：US17370673

申请日：2021-07-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chin-Shan Wang ,  Shun-Yi Lee

IPC分类号： H01L27/108 ,  H01L21/00 ,  H10B12/00 ,  H01L21/8238

CPC分类号： H10B12/373 ,  H10B12/03 ,  H10B12/0387 ,  H10B12/056 ,  H10B12/36 ,  H10B12/488 ,  H01L21/823878

摘要： A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.

公开(公告)号：US20230403841A1

公开(公告)日：2023-12-14

申请号：US18093969

申请日：2023-01-06

申请人： Changxin Memory Technologies, Inc.

发明人： Daohuan FENG ,  Xiaojie LI

IPC分类号： H10B12/00

CPC分类号： H10B12/056

摘要： A semiconductor structure manufacturing method includes: providing a substrate and forming a groove in the substrate; forming a barrier layer on a sidewall of the groove; epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and removing a portion of the intermediate structure and a portion of the substrate to form a fin structure.

公开(公告)号：US20230354583A1

公开(公告)日：2023-11-02

申请号：US18219722

申请日：2023-07-10

申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Janbo Zhang ,  Li-Wei Feng ,  Yu-Cheng Tung

IPC分类号： H10B12/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC分类号： H10B12/36 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6656 ,  H10B12/056

摘要： The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

公开(公告)号：US11785759B2

公开(公告)日：2023-10-10

申请号：US17894968

申请日：2022-08-24

申请人： Intel Corporation

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

CPC分类号： H10B12/20 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/7851 ,  H10B12/00 ,  H10B12/01 ,  H10B12/36 ,  H10B12/056 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.