公开(公告)号：US12125850B2

公开(公告)日：2024-10-22

申请号：US17234256

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78 ,  H10B12/00 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/785 ,  H10B12/31 ,  H10B12/36 ,  H01L27/0924 ,  H10B12/34 ,  H10B12/37

摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20240215267A1

公开(公告)日：2024-06-27

申请号：US18596623

申请日：2024-03-06

申请人： Monolithic 3D Inc.

发明人： Deepak C. Sekar ,  Zvi Or-Bach

IPC分类号： H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/105 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10B61/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

摘要： A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

公开(公告)号：US11943912B2

公开(公告)日：2024-03-26

申请号：US17844111

申请日：2022-06-20

申请人： SK hynix Inc.

发明人： Dong-Soo Kim

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00 ,  H01L21/3105

CPC分类号： H10B12/34 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/32136 ,  H01L21/32155 ,  H01L21/76224 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785 ,  H10B12/053 ,  H10B12/056 ,  H10B12/36 ,  H01L21/31053 ,  H01L29/517

摘要： A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.

公开(公告)号：US11916149B2

公开(公告)日：2024-02-27

申请号：US17814330

申请日：2022-07-22

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30 ,  H10B12/00 ,  H01L49/02

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor. The capacitor additionally comprises a polar layer comprising a base polar material doped with a dopant, wherein the base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The semiconductor device additionally comprises a lower barrier layer comprising a refractory metal or an intermetallic compound between the lower conductive oxide electrode and the conductive via.

公开(公告)号：US11895824B2

公开(公告)日：2024-02-06

申请号：US17667498

申请日：2022-02-08

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Gilbert Dewey ,  Abhishek A Sharma

IPC分类号： H10B12/00

CPC分类号： H10B12/36 ,  H10B12/056

摘要： A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

公开(公告)号：US11832441B2

公开(公告)日：2023-11-28

申请号：US17533451

申请日：2021-11-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Sheng-Hui Yang

IPC分类号： H01L29/78 ,  H10B12/00 ,  H01L29/66 ,  H01L29/417

CPC分类号： H10B12/36 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure.

公开(公告)号：US11757043B2

公开(公告)日：2023-09-12

申请号：US17819601

申请日：2022-08-12

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US20230155029A1

公开(公告)日：2023-05-18

申请号：US17815100

申请日：2022-07-26

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30

CPC分类号： H01L29/78618 ,  H01L29/6684 ,  H01L29/2003 ,  H01L29/7408 ,  H01L29/7869 ,  H01L29/7375 ,  H01L28/65 ,  H01L28/56 ,  H01L28/57 ,  H10B53/30 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a capacitor comprises a crystalline polar layer comprising a base polar material substitutionally doped with a dopant. The base polar material comprises one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element of one of 4d series, 5d series, 4f series or 5f series that is different from the one or more metal elements, such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV.

公开(公告)号：US20240349488A1

公开(公告)日：2024-10-17

申请号：US18751360

申请日：2024-06-24

申请人： SK hynix Inc.

发明人： Seung Wook RYU ,  Wan Sup SHIN

IPC分类号： H10B12/00

CPC分类号： H10B12/36

摘要： A semiconductor memory device includes: a conductive line stack including a plurality of first conductive lines that are stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive pads extending laterally from edge portions of the first conductive lines, respectively; and contact plugs coupled to the conductive pads, respectively.

公开(公告)号：US20240339537A1

公开(公告)日：2024-10-10

申请号：US18744888

申请日：2024-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mark van Dal ,  Martin Christopher Holland ,  Matthias Passlack

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H10B12/00

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/66795 ,  H10B12/36

摘要： A semiconductor device includes a fin protruding upwardly from a substrate. The fin includes a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls. The semiconductor device also includes a two-dimensional material layer disposed on the first and second sidewalls of the fin without being disposed on the top surface of the fin, and a gate stack disposed on the fin. The gate stack contacts a channel region defined in the two-dimensional material layer. The two-dimensional material layer includes a flat portion extending laterally away from the fin.