公开(公告)号：US20210109839A1

公开(公告)日：2021-04-15

申请号：US17128291

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/24 ,  G06F9/38 ,  G06F15/78

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US20220197643A1

公开(公告)日：2022-06-23

申请号：US17133618

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F9/30 ,  G06F12/0875

Abstract: Methods and apparatus relating to speculative decompression within processor core caches are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into a plurality of cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the plurality of cachelines of the cache of the processor core in response to the second micro operation. The decompression instruction causes the DE circuitry to perform an out-of-order decompression of the plurality of cachelines. Other embodiments are also disclosed and claimed.

公开(公告)号：US10754655B2

公开(公告)日：2020-08-25

申请号：US16021838

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Hong Wang ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz

IPC: G06F9/32 ,  G06F9/42 ,  G06F9/38 ,  G06F9/30

Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

公开(公告)号：US20220197799A1

公开(公告)日：2022-06-23

申请号：US17133615

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0895 ,  G06F9/38

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200004542A1

公开(公告)日：2020-01-02

申请号：US16021838

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz ,  Hong Wang

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

公开(公告)号：US11656971B2

公开(公告)日：2023-05-23

申请号：US17582051

申请日：2022-01-24

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F11/30 ,  G06F15/78 ,  G06F9/24 ,  G06F9/38

CPC classification number: G06F11/3476 ,  G06F9/24 ,  G06F9/3836 ,  G06F11/3024 ,  G06F11/3055 ,  G06F15/7875

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US20220206925A1

公开(公告)日：2022-06-30

申请号：US17582051

申请日：2022-01-24

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F9/24 ,  G06F9/38 ,  G06F11/30 ,  G06F15/78

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US20220197813A1

公开(公告)日：2022-06-23

申请号：US17133624

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F12/0875 ,  G06F12/0813 ,  G06F12/0811 ,  G06F12/1045

Abstract: Methods and apparatus relating to techniques for increasing per core memory bandwidth by using forget store operations are described. In an embodiment, a cache stores a buffer. Execution circuitry executes an instruction. The instruction causes one or more cachelines in the cache to be marked based on a start address for the buffer and a size of the buffer. A marked cacheline in the cache is to be prevented from being written back to memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US10915421B1

公开(公告)日：2021-02-09

申请号：US16575535

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F15/78 ,  G06F11/30 ,  G06F9/38 ,  G06F9/24

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US12182018B2

公开(公告)日：2024-12-31

申请号：US17133615

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Adarsh Chauhan ,  Vinodh Gopal ,  Vedvyas Shanbhogue ,  Sreenivas Subramoney ,  Wajdi Feghali

IPC: G06F12/0811 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0895

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.