公开(公告)号：US10754655B2

公开(公告)日：2020-08-25

申请号：US16021838

申请日：2018-06-28

申请人： Intel Corporation

发明人： Adarsh Chauhan ,  Hong Wang ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz

IPC分类号： G06F9/32 ,  G06F9/42 ,  G06F9/38 ,  G06F9/30

摘要： A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

公开(公告)号：US20160364239A1

公开(公告)日：2016-12-15

申请号：US15121348

申请日：2014-03-27

申请人： INTEL CORPORATION

发明人： Anton Lechenko ,  Andrey Efimov ,  Sergey Y. Shishlov ,  Andrey Kluchnikov ,  Kamil Garifullin ,  Igor Burovenko ,  Boris A. Babayan

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3855 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3857

摘要： A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

摘要翻译： 处理器包括执行无序指令流的逻辑。 指令流被分成多个线，并且其指令和流内的指令按程序顺序（PO）排序。 处理器还包括用于识别指令流中最旧的未分配指令并将其相关联的PO记录为执行的指令指针的逻辑，识别指令流中最近提交的存储指令并将其相关联的PO记录为存储承诺指针，搜索 具有PO的指针小于执行指令指针，在具有PO小于搜索指针的PO的存储缓冲器中识别第一组存储指令，并且有资格进行承诺，评估第一组存储指令是否大于多个读取端口 存储缓冲区，并调整搜索指针。

公开(公告)号：US10514927B2

公开(公告)日：2019-12-24

申请号：US15121348

申请日：2014-03-27

申请人： Intel Corporation

发明人： Anton Lechanka ,  Andrey Efimov ,  Sergey Y. Shishlov ,  Andrey Kluchnikov ,  Kamil Garifullin ,  Igor Burovenko ,  Boris A. Babayan

IPC分类号： G06F9/30 ,  G06F9/38

摘要： A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

公开(公告)号：US09552169B2

公开(公告)日：2017-01-24

申请号：US14706936

申请日：2015-05-07

申请人： INTEL CORPORATION

发明人： Lihu Rappoport ,  Jared W. Stark ,  Kamil Garifullin ,  Franck Sala ,  Pavel I. Kryukov ,  Stanislav Shwartsman

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F3/0631 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0671 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F12/0802

摘要： A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

摘要翻译： 描述了使用虚拟寄存器进行有效的存储器重命名预测的方法和装置。 例如，设备的一个实施例包括：存储器执行单元（MEU），用于执行存储和加载操作，以分别将存储数据存储到存储器中并从存储器加载数据; 分配给存储和加载操作的多个存储器重命名（MRN）寄存器，每个MRN寄存器存储与存储操作相关联的数据，使得数据可用于后续加载操作; 以及至少一个MRN预测器，其包括用于向每个MRN寄存器分配虚拟存储器重命名（VMRN）寄存器的数据结构，MRN预测器，使用标识MRN的值来响应于负载和/或存储操作来查询数据结构 分配给负载和/或存储操作的寄存器，以确定与负载和/或存储操作相关联的当前VMRN寄存器。

公开(公告)号：US20200004542A1

公开(公告)日：2020-01-02

申请号：US16021838

申请日：2018-06-28

申请人： Intel Corporation

发明人： Adarsh Chauhan ,  Jayesh Gaur ,  Zeev Sperber ,  Sumeet Bandishte ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Kamil Garifullin ,  Sreenivas Subramoney ,  Adi Yoaz ,  Hong Wang

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

申请人： Intel Corporation

发明人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.