公开(公告)号：US20230094696A1

公开(公告)日：2023-03-30

申请号：US17484060

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carlos Nava Rodriguez ,  Jonathan Hersh ,  Aditi Gautam ,  Yoav Harel ,  Benjamin Pletcher ,  Michael Apodaca

IPC: G06T15/00 ,  G06F12/0895 ,  G06T1/60

Abstract: Embodiments described herein are generally directed to a local cache structure within a shared function of a 3D pipeline that facilitates efficient caching of resource state. In an example, the cache structure is maintained within a sub-core of a GPU. The local cache structure includes (i) an SC having entries each containing a state of a binded resource, and (ii) a DSAT having entries each containing an index into the SC. The DSAT is tagged by SBTO values representing addresses of entries of a binding table. A request, including information indicative of an SBTO pointing to an entry within the binding table, is received for a state of a particular binded resource being accessed by a shared function of the 3D pipeline. Based on the SBTO and during a single access to the cache structure, a determination is made regarding whether the state of the particular binded resource is present.