公开(公告)号：US09489707B2

公开(公告)日：2016-11-08

申请号：US14039135

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Hema Chand Nalluri ,  Joy Chandra ,  Prosun Chatterjee ,  Benjamin Pletcher ,  Yoav Harel ,  Steven Spangler

IPC: G06F13/14 ,  G06F15/00 ,  G06T1/00 ,  G06T1/20 ,  G06F3/00 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F3/00 ,  G06F9/5083 ,  G06T2200/28

Abstract: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.

Abstract translation: 本文描述的实施例包括图形处理单元。 图形处理单元包括多个执行单元。 图形处理单元还包括多个采样器单元。 每个采样器单元对应于采样器调度逻辑单元和至少一个执行单元，并且采样器调度逻辑单元用于网络多个采样器单元。

公开(公告)号：US11281463B2

公开(公告)日：2022-03-22

申请号：US15935037

申请日：2018-03-25

Applicant: Intel Corporation

Inventor： Benjamin Pletcher ,  Rahul Kumar

IPC: G06F9/30 ,  H03M7/24 ,  G06F5/01 ,  G06F7/483 ,  G06N3/08 ,  G06N3/063

Abstract: Methods and apparatus relating to conversion of an unsigned normalized (unorm) integer values to floating-point (float) values in low power are described. In an embodiment, conversion logic converts a unorm integer value to a floating-point value based on detection of whether the unorm integer matches one of three cases, wherein the unorm integer value comprises n bits. Memory stores a count value corresponding to n−1 bits of the unorm integer value after detection of a leading 1 in the unorm integer value. The three cases include: a first case with all zeros, a second case with all ones, and a third case with a combination of one or more zeros and one or more ones. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230111571A1

公开(公告)日：2023-04-13

申请号：US17484619

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carlos Nava Rodriguez ,  Benjamin Pletcher ,  Yoav Harel ,  Bret Martin ,  Sudarshanram Shetty

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/04

Abstract: Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.

公开(公告)号：US20230094696A1

公开(公告)日：2023-03-30

申请号：US17484060

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carlos Nava Rodriguez ,  Jonathan Hersh ,  Aditi Gautam ,  Yoav Harel ,  Benjamin Pletcher ,  Michael Apodaca

IPC: G06T15/00 ,  G06F12/0895 ,  G06T1/60

Abstract: Embodiments described herein are generally directed to a local cache structure within a shared function of a 3D pipeline that facilitates efficient caching of resource state. In an example, the cache structure is maintained within a sub-core of a GPU. The local cache structure includes (i) an SC having entries each containing a state of a binded resource, and (ii) a DSAT having entries each containing an index into the SC. The DSAT is tagged by SBTO values representing addresses of entries of a binding table. A request, including information indicative of an SBTO pointing to an entry within the binding table, is received for a state of a particular binded resource being accessed by a shared function of the 3D pipeline. Based on the SBTO and during a single access to the cache structure, a determination is made regarding whether the state of the particular binded resource is present.

公开(公告)号：US20190042246A1

公开(公告)日：2019-02-07

申请号：US15935037

申请日：2018-03-25

Applicant: Intel Corporation

Inventor： Benjamin Pletcher ,  Rahul Kumar

IPC: G06F9/30 ,  H03M7/24 ,  G06F7/483

Abstract: Methods and apparatus relating to conversion of an unsigned normalized (unorm) integer values to floating-point (float) values in low power are described. In an embodiment, conversion logic converts a unorm integer value to a floating-point value based on detection of whether the unorm integer matches one of three cases, wherein the unorm integer value comprises n bits. Memory stores a count value corresponding to n−1 bits of the unorm integer value after detection of a leading 1 in the unorm integer value. The three cases include: a first case with all zeros, a second case with all ones, and a third case with a combination of one or more zeros and one or more ones. Other embodiments are also disclosed and claimed.