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    DYNAMICALY ADJUSTED CACHE POLICY AND COMPRESSION SCHEME FOR GRAPHS PROCESSED BY GRAPH NEURAL NETWORKS
    3.
    发明申请
    DYNAMICALY ADJUSTED CACHE POLICY AND COMPRESSION SCHEME FOR GRAPHS PROCESSED BY GRAPH NEURAL NETWORKS 有权

    公开(公告)号：US20220261357A1

    公开(公告)日：2022-08-18

    申请号：US17734994

    申请日：2022-05-02

    Applicant: Intel Corporation

    Inventor： Ronen Gabbai ,  Amit Bleiweiss ,  Ohad Falik ,  Amit Gur ,  Almog Tzabary

    IPC: G06F12/128 ,  G06F12/0891 ,  G06F12/126 ,  G06K9/62

    Abstract: Systems, apparatuses, and methods include technology that determines, with a neural network, that a first eviction node stored in a cache will be evicted from the cache based on a cache policy. The first eviction node is part of a plurality of nodes associated with a graph. Further, a subset of nodes of the plurality of nodes remains in the cache after the eviction of the first eviction node from the cache. The technology further tracks a number of cache hits on the cache during an aggregation operation associated with a hardware accelerator, where the aggregation operation is executed on the subset of nodes that remain in the cache after the eviction of the eviction node from the cache. The technology executes a training process on the neural network to adjust the cache policy based on the number of the cache hits.

    Compiler guided power allocation in computing devices
    4.
    发明授权
    Compiler guided power allocation in computing devices 有权

    公开(公告)号：US11079825B2

    公开(公告)日：2021-08-03

    申请号：US16539138

    申请日：2019-08-13

    Applicant: Intel Corporation

    Inventor： Anat Heilper ,  Eran Dagan ,  Amit Bleiweiss ,  Amit Gur

    IPC: G06F1/3206 ,  G06N3/06 ,  G06F1/3234 ,  G06F1/3296

    Abstract: Apparatus, devices, systems, methods, and articles of manufacture are disclosed to allocate power in a computing device. An example system includes a compiler to: analyze power consumption behavior of power consumption units of the computing device; build a power profile; and generate source code with hints of the power profile. The example system includes a power control circuit to: develop a power policy using the hints of the power profile and requests for power licenses from the power consumption units of the computing device; and allocate power to the power consumption units based on the power profile.

    AUTONOMOUS C-STATE ALGORITHM AND COMPUTATIONAL ENGINE ALIGNMENT FOR IMPROVED PROCESSOR POWER EFFICIENCY
    6.
    发明申请
    AUTONOMOUS C-STATE ALGORITHM AND COMPUTATIONAL ENGINE ALIGNMENT FOR IMPROVED PROCESSOR POWER EFFICIENCY 审中-公开

    公开(公告)号：US20190011976A1

    公开(公告)日：2019-01-10

    申请号：US16130916

    申请日：2018-09-13

    Applicant: Intel Corporation

    Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

    IPC: G06F1/32

    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

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