公开(公告)号：US20240111826A1

公开(公告)日：2024-04-04

申请号：US17937252

申请日：2022-09-30

申请人： Intel Corporation

发明人： Jiasheng Chen ,  Kevin Hurd ,  Changwon Rhee ,  Jorge Parra ,  Fangwen Fu ,  Theo Drane ,  William Zorn ,  Peter Caday ,  Gregory Henry ,  Guei-Yuan Lueh ,  Farzad Chehrazi ,  Amit Karande ,  Turbo Majumder ,  Xinmin Tian ,  Milind Girkar ,  Hong Jiang

IPC分类号： G06F17/16 ,  G06F7/544 ,  G06T1/20

CPC分类号： G06F17/16 ,  G06F7/5443 ,  G06T1/20

摘要： An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.