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    DETERMINISTIC BROADCASTING FROM SHARED MEMORY
    1.
    发明公开
    DETERMINISTIC BROADCASTING FROM SHARED MEMORY 审中-公开

    公开(公告)号：US20240111534A1

    公开(公告)日：2024-04-04

    申请号：US17957486

    申请日：2022-09-30

    申请人： Intel Corporation

    发明人： Fangwen Fu ,  Chunhui Mei ,  Maxim Kazakov ,  Biju George ,  Jorge Parra ,  Supratim Pal

    IPC分类号： G06F9/30 ,  G06F9/54

    CPC分类号： G06F9/30047 ,  G06F9/3009 ,  G06F9/542

    摘要： Embodiments described herein provide a technique enable a broadcast load from an L1 cache or shared local memory to register files associated with hardware threads of a graphics core. One embodiment provides a graphics processor comprising a cache memory and a graphics core coupled with the cache memory. The graphics core includes a plurality of hardware threads and memory access circuitry to facilitate access to memory by the plurality of hardware threads. The graphics core is configurable to process a plurality of load request from the plurality of hardware threads, detect duplicate load requests within the plurality of load requests, perform a single read from the cache memory in response to the duplicate load requests, and transmit data associated with the duplicate load requests to requesting hardware threads.

    Computing efficient cross channel operations in parallel computing machines using systolic arrays
    5.
    发明授权
    Computing efficient cross channel operations in parallel computing machines using systolic arrays 有权

    公开(公告)号：US12093213B2

    公开(公告)日：2024-09-17

    申请号：US18310129

    申请日：2023-05-01

    申请人： Intel Corporation

    发明人： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Chandra Gurram

    IPC分类号： G06F15/80 ,  G06F17/16 ,  G06N20/00

    CPC分类号： G06F15/8046 ,  G06F15/8007 ,  G06F17/16 ,  G06N20/00

    摘要： An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.