公开(公告)号：US20250124266A1

公开(公告)日：2025-04-17

申请号：US18989154

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Kamlesh Pillai ,  Gurpreet S. Kalsi ,  Amit Mishra

IPC: G06N3/048 ,  G06F7/499 ,  G06F7/556 ,  G06F17/11 ,  G06F17/17 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.

公开(公告)号：US20220198735A1

公开(公告)日：2022-06-23

申请号：US17128708

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Raghavendra Kamath Miyar ,  Sudheendra Srivathsa ,  Krishan Malik ,  Narsim Krishna ,  Rajalakshmi Athimoolam ,  Amit Mishra

IPC: G06T15/00 ,  G06T11/40 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.

公开(公告)号：US11775805B2

公开(公告)日：2023-10-03

申请号：US16023441

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kamlesh Pillai ,  Gurpreet S. Kalsi ,  Amit Mishra

IPC: G06N3/048 ,  G06F17/11 ,  G06N3/063 ,  G06F7/499 ,  G06F7/556 ,  G06N3/084 ,  G06F17/17 ,  G06N3/045 ,  G06N3/044

CPC classification number: G06N3/048 ,  G06F7/49957 ,  G06F7/556 ,  G06F17/11 ,  G06F17/17 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044

Abstract: A log circuit for piecewise linear approximation is disclosed. The log circuit identifies an input associated with a logarithm operation to be performed using piecewise linear approximation. The log circuit then identifies a range that the input falls within from various ranges associated with piecewise linear approximation (PLA) equations for the logarithm operation, where the identified range corresponds to one of the PLA equations. The log circuit computes a result of the corresponding PLA equation based on the respective operands of the equation. The log circuit then returns an output associated with the logarithm operation, which is based at least partially on the result of the PLA equation.

公开(公告)号：US12217155B2

公开(公告)日：2025-02-04

申请号：US18455026

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Kamlesh Pillai ,  Gurpreet S. Kalsi ,  Amit Mishra

IPC: G06N3/048 ,  G06F7/499 ,  G06F7/556 ,  G06F17/11 ,  G06F17/17 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.

公开(公告)号：US20240020518A1

公开(公告)日：2024-01-18

申请号：US18455026

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Kamlesh Pillai ,  Gurpreet S. Kalsi ,  Amit Mishra

IPC: G06N3/048 ,  G06F17/11 ,  G06F7/499 ,  G06N3/063 ,  G06F7/556 ,  G06N3/084 ,  G06F17/17 ,  G06N3/045

CPC classification number: G06N3/048 ,  G06F17/11 ,  G06F7/49957 ,  G06N3/063 ,  G06F7/556 ,  G06N3/084 ,  G06F17/17 ,  G06N3/045 ,  G06N3/044

Abstract: In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.