公开(公告)号：US20230237230A1

公开(公告)日：2023-07-27

申请号：US18191789

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  Byron Sinclair ,  Deshanand P. Singh ,  Scott Jeremy Weber ,  Anandh Venkateswaran ,  Mahesh A. Iyer

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347 ,  G06F2119/12

Abstract: Systems or methods of the present disclosure may provide a library including multiple personas that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more personas to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The personas may be loaded into one or more regions of the integrated circuit device to realize the design. That is, the design may be realized by one persona may be implemented across multiple regions, one region may be configured by multiple personas, one persona configuring one region, or any combination thereof. Additionally or alternatively, the integrated circuit device may include networks-on-chip to improve data routing between the regions.