公开(公告)号：US20240020449A1

公开(公告)日：2024-01-18

申请号：US18475512

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  Deshanand P. Singh ,  Gregg William Baeckler ,  Mahesh A. Iyer ,  Michael Kinsner ,  Chengping Liang ,  Victor Tzi-on Zhang

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design. For example, a design may be mapped to one or more macros in the library, and the one or more macros may be placed into and routed between a portion of a region, one region, one or more regions of the integrated circuit device to implement the design. Since the macros may be pre-compiled, compilation time experienced by the designer may correspond to the placement and routing of the one or more macros, which may be less than compilation time for fine-grained operations. The pre-compiled logic within the macros may be set using a lookup table mask to set and/or adjust a functionality of the macro. Additionally or alternatively, the place and route operation may be performed at finer granularities to reduce bottle necks.

公开(公告)号：US20230237231A1

公开(公告)日：2023-07-27

申请号：US18191785

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  Michael Kinsner ,  Gabriel Quan ,  Victor Tzi-on Zhang ,  Mahesh A. Iyer ,  Chengping Liang ,  Deshanand P. Singh

IPC: G06F30/347 ,  G06F30/31

CPC classification number: G06F30/347 ,  G06F30/31

Abstract: Systems or methods of the present disclosure may provide an electronic device that includes memory storing instructions; and a processor, that when executing the instructions, is to receive a design for a programmable fabric of an integrated circuit device. The instructions are also to cause the processor to cause compilation of the design into a configuration during a compilation window. The instructions further are to cause the processor to determine at least some routing for the configuration outside of the compilation window.

公开(公告)号：US20230237230A1

公开(公告)日：2023-07-27

申请号：US18191789

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  Byron Sinclair ,  Deshanand P. Singh ,  Scott Jeremy Weber ,  Anandh Venkateswaran ,  Mahesh A. Iyer

IPC: G06F30/343 ,  G06F30/347

CPC classification number: G06F30/343 ,  G06F30/347 ,  G06F2119/12

Abstract: Systems or methods of the present disclosure may provide a library including multiple personas that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more personas to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The personas may be loaded into one or more regions of the integrated circuit device to realize the design. That is, the design may be realized by one persona may be implemented across multiple regions, one region may be configured by multiple personas, one persona configuring one region, or any combination thereof. Additionally or alternatively, the integrated circuit device may include networks-on-chip to improve data routing between the regions.