公开(公告)号：US20220123753A1

公开(公告)日：2022-04-21

申请号：US17561157

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Ping-Chen Liu ,  Andy Lee

IPC: H03K19/173 ,  H03K19/094 ,  H03K19/177

Abstract: Systems and methods of the present disclosure may provide efficient power consumption for programmable logic devices based on unused portions of programmable logic. A programmable logic device includes a plurality of programmable logic sectors that implement a circuit design, unused portions of the programmable logic device, and interconnection resources. The interconnection resources include a multiplexer that receives a control signal and that generates an output signal based on the control signal and a driver that receives the output signal and that implements a low-power mode to reduce leakage current.

公开(公告)号：US20230410897A1

公开(公告)日：2023-12-21

申请号：US18241217

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： David Parkhouse ,  Andy Lee ,  J M Lewis Higgins ,  Yan Cui ,  Shuxian Chen ,  Shankar Sinha

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.