公开(公告)号：US09922702B1

公开(公告)日：2018-03-20

申请号：US15397035

申请日：2017-01-03

Applicant: Intel Corporation

Inventor： Amarnath Shanmugam ,  Anik Basu ,  Steve P. Ferrera ,  Srinivas Rajamani ,  Feroze A. Merchant

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  H03K19/20

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  H03K19/20

Abstract: Described is an apparatus which comprises: a pass-gate; a sleep transistor configured as a diode-connected device controllable by the pass-gate; and a word-line driver coupled to the sleep transistor and the pass-gate.

公开(公告)号：US20230170012A1

公开(公告)日：2023-06-01

申请号：US17538478

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Steve P. Ferrera ,  Mauricio J. Valverde Monge ,  Anik Basu ,  Feroze Merchant

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  H03K19/173 ,  H03K19/20

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4085 ,  H03K19/1737 ,  H03K19/20

Abstract: Embodiments herein relate to circuitry which allows data to be processed and written back within an SRAM device. In a toggle operation, a memory cell is read and the bit at the complementary output node of a sense amplifier is written back to the memory cell. In a copy operation, a memory cell is read and the bit at the primary output node of the sense amplifier is written to another memory cell in the column. In another aspect, logic operations such as AND, OR, majority, AND-OR, OR-AND, and associated inverse operations can be performed within the SRAM device. This can involve writing data to one or more control memory cells in the same column as the data memory cells involved in the logic operation, and setting the respective word lines to be active concurrently.