公开(公告)号：US20240273028A1

公开(公告)日：2024-08-15

申请号：US18600496

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Corey D. GOUGH ,  Yuval BUSTAN ,  Arvind RAMAN ,  Mariusz ORIOL ,  Nilanjan PALIT ,  Philip ABRAHAM ,  Priyanka GANESH ,  Daniel G. CARTAGENA ,  Mateusz DUCHALSKI

IPC: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

CPC classification number: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

Abstract: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.

公开(公告)号：US20220206875A1

公开(公告)日：2022-06-30

申请号：US17134065

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Jeff A. HUXEL ,  Jeffrey G. WIEDEMEIER ,  James D. ALLEN ,  Arvind RAMAN ,  Krishnakumar GANAPATHY

IPC: G06F9/52 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

公开(公告)号：US20240370312A1

公开(公告)日：2024-11-07

申请号：US18775652

申请日：2024-07-17

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Jeff A. HUXEL ,  Jeffrey G. WIEDEMEIER ,  James D. ALLEN ,  Arvind RAMAN ,  Krishnakumar GANAPATHY

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F11/07 ,  G06F11/16

Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.