公开(公告)号：US20250005159A1

公开(公告)日：2025-01-02

申请号：US18217484

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Avinash CHANDRASEKARAN ,  Murugasamy K. NACHIMUTHU ,  Mariusz ORIOL ,  Piotr MATUSZCZAK

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/44

Abstract: An apparatus and method are described for staging and activating microcode of a processor. For example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (MCU); a plurality of MCU staging memories, each MCU staging memory to temporarily store one or more of the MCUs for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.

公开(公告)号：US20250103380A1

公开(公告)日：2025-03-27

申请号：US18973872

申请日：2024-12-09

Applicant: Intel Corporation

Inventor： Kasper WSZOLEK ,  Janusz JURSKI ,  Mariusz ORIOL ,  Matthew James ADILETTA

IPC: G06F9/455 ,  G06F13/38 ,  G06F13/42

Abstract: Examples described herein relate to at least one processor that is to communicate with a management controller to communicate with multiple interfaces. In some examples, wherein at least two of the multiple interfaces are to provide boot firmware code to the at least one processor and a connection interface.

公开(公告)号：US20220197859A1

公开(公告)日：2022-06-23

申请号：US17690950

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Janusz JURSKI ,  Myron LOEWEN ,  Mariusz ORIOL ,  Patrick SCHOELLER ,  Jerry BACKER ,  Richard Marian THOMAIYAR ,  Eliel LOUZOUN ,  Piotr MATUSZCZAK

IPC: G06F15/82 ,  G06F21/62

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices. The tunneled connections may employ encapsulated messages with outer and inner headers and/or augmented MCTP messages with repurposed fields used to store source and destination EIDs.

公开(公告)号：US20240241778A1

公开(公告)日：2024-07-18

申请号：US18562237

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Ugonna ECHERUO ,  Reza E. DAFTARI ,  Theodros YIGZAW ,  Mariusz ORIOL

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/079 ,  G06F11/0793

Abstract: A system (204) can respond to detection of an uncorrectable error (UE) (254) in memory (246) based on fault-aware analysis. The fault-aware analysis enables the system (204) to generate a determination of a specific hardware element of the memory (246) that caused the detected UE (254). In response to detection of a UE (254), the system (204) can correlate a hardware configuration (256) of the memory (246) device with historical data indicating memory (246) faults for hardware elements of the hardware configuration (256). Based on a determination of the specific component that likely caused the UE (254), the system (204) can issue a corrective action for the specific hardware element based on the determination.

公开(公告)号：US20240054039A1

公开(公告)日：2024-02-15

申请号：US18258298

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vasudevan SRINIVASAN ,  Knut GRIMSRUD ,  Johan VAN DE GROENENDAAL ,  Mariusz ORIOL ,  Nishi AHUJA ,  Shen ZHOU ,  Samantha ALT ,  Katalin BARTFAI-WALCOTT ,  Arkadiusz BERENT

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/076

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.

公开(公告)号：US20240273028A1

公开(公告)日：2024-08-15

申请号：US18600496

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Corey D. GOUGH ,  Yuval BUSTAN ,  Arvind RAMAN ,  Mariusz ORIOL ,  Nilanjan PALIT ,  Philip ABRAHAM ,  Priyanka GANESH ,  Daniel G. CARTAGENA ,  Mateusz DUCHALSKI

IPC: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

CPC classification number: G06F12/0842 ,  G06F1/3206 ,  G06F1/3293 ,  G06F12/084

Abstract: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.

公开(公告)号：US20230083193A1

公开(公告)日：2023-03-16

申请号：US17348435

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Xiaoming DU ,  Cong LI ,  Kuljit S. BAINS ,  Rajat AGARWAL ,  Murugasamy K. NACHIMUTHU ,  Maciej LAWNICZAK ,  Chao Yan TANG ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

公开(公告)号：US20210279122A1

公开(公告)日：2021-09-09

申请号：US17317745

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Xiaoming DU ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.