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1.
公开(公告)号:US20250111579A1
公开(公告)日:2025-04-03
申请号:US18915640
申请日:2024-10-15
Applicant: Intel Corporation
Inventor: Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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公开(公告)号:US20220092741A1
公开(公告)日:2022-03-24
申请号:US17487882
申请日:2021-09-28
Applicant: INTEL CORPORATION
Inventor: Zhengmin LI , Atsuo KUWAHARA , Deepak VEMBAR
Abstract: An apparatus and method for efficiently improving virtual/real interactions in augmented reality. For example, one embodiment of a method comprises: capturing a raw image including depth data; identifying one or more regions of interest based on a detected spatial proximity of one or more virtual objects and one or more real objects; generating a super-resolution map of the one or more regions of interest using machine-learning techniques or results thereof; detecting interactions between the virtual objects and the real objects using the super-resolution map; and performing one or more graphics processing or general purpose processing operations based on the detected interactions.
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3.
公开(公告)号:US20240046403A1
公开(公告)日:2024-02-08
申请号:US18231379
申请日:2023-08-08
Applicant: Intel Corporation
Inventor: Michael DOYLE , Travis SCHLUESSLER , Gabor LIKTOR , Atsuo KUWAHARA , Jefferson AMSTUTZ
IPC: G06T1/20 , G06F16/901 , G06F9/38 , G06F9/50 , G06T15/00
CPC classification number: G06T1/20 , G06F16/9027 , G06F9/3877 , G06F9/3891 , G06F9/5077 , G06T15/005 , G06T15/06
Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.
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4.
公开(公告)号:US20210287419A1
公开(公告)日:2021-09-16
申请号:US17159399
申请日:2021-01-27
Applicant: Intel Corporation
Inventor: Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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5.
公开(公告)号:US20240013470A1
公开(公告)日:2024-01-11
申请号:US18371614
申请日:2023-09-22
Applicant: Intel Corporation
Inventor: Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
CPC classification number: G06T15/005 , G06T1/60 , G06T15/06 , G06T2210/21
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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6.
公开(公告)号:US20220414970A1
公开(公告)日:2022-12-29
申请号:US17868618
申请日:2022-07-19
Applicant: Intel Corporation
Inventor: Gabor LIKTOR , Karthik VAIDYANATHAN , Jefferson AMSTUTZ , Atsuo KUWAHARA , Michael DOYLE , Travis SCHLUESSLER
Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.
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公开(公告)号:US20200184602A1
公开(公告)日:2020-06-11
申请号:US16685348
申请日:2019-11-15
Applicant: INTEL CORPORATION
Inventor: Zhengmin LI , Atsuo KUWAHARA , Deepak VEMBAR
Abstract: An apparatus and method for efficiently improving virtual/real interactions in augmented reality. For example, one embodiment of a method comprises: capturing a raw image including depth data; identifying one or more regions of interest based on a detected spatial proximity of one or more virtual objects and one or more real objects; generating a super-resolution map of the one or more regions of interest using machine-learning techniques or results thereof; detecting interactions between the virtual objects and the real objects using the super-resolution map; and performing one or more graphics processing or general purpose processing operations based on the detected interactions.
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