公开(公告)号：US20240248722A1

公开(公告)日：2024-07-25

申请号：US18626629

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20230273795A1

公开(公告)日：2023-08-31

申请号：US18311810

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20180276027A1

公开(公告)日：2018-09-27

申请号：US15899664

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Atul KHARE ,  Leena PUTHIYEDATH ,  Asit MALLICK ,  Jim COKE ,  Michael MISHAELI ,  Gilbert NEIGER ,  Vivekananthan SANJEEPAN ,  Jason BRANDT

IPC: G06F9/46 ,  G06F9/30

CPC classification number: G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101 ,  H05K999/99

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.