公开(公告)号：US11256287B2

公开(公告)日：2022-02-22

申请号：US16440890

申请日：2019-06-13

Applicant: Intel Corporation

Inventor： Nathaniel August ,  Muhammed Elgousi ,  Benjamin Gordon ,  Tsai-Yuan Chen

IPC: G06F1/12 ,  H03L7/14 ,  H03B5/32 ,  H03L7/08

Abstract: Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.