Apparatus and method to maintain stable clocking

    公开(公告)号:US11256287B2

    公开(公告)日:2022-02-22

    申请号:US16440890

    申请日:2019-06-13

    Abstract: Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.

    HARMONIC TRAPPING TECHNIQUES FOR TRANSMITTER INTERSTAGE MATCHING

    公开(公告)号:US20230198479A1

    公开(公告)日:2023-06-22

    申请号:US17559341

    申请日:2021-12-22

    CPC classification number: H03F3/21 H03F3/005 H03F1/26 H03F2200/372

    Abstract: A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.

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