公开(公告)号：US20220004495A1

公开(公告)日：2022-01-06

申请号：US17475984

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Chace Clark ,  Francis Corrado ,  Shivashekar Muralishankar ,  Suresh Nagarajan

IPC: G06F12/0802 ,  G06F3/06

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

公开(公告)号：US20190042452A1

公开(公告)日：2019-02-07

申请号：US16143734

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Chace Clark ,  Francis Corrado

IPC: G06F12/0888 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/16 ,  G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

公开(公告)号：US11003582B2

公开(公告)日：2021-05-11

申请号：US16143734

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Chace Clark ,  Francis Corrado

IPC: G06F12/0888 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/16 ,  G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

公开(公告)号：US10915264B2

公开(公告)日：2021-02-09

申请号：US16381914

申请日：2019-04-11

Applicant: Intel Corporation

Inventor： Jason Akers ,  Chace Clark

IPC: G06F3/06

Abstract: Embodiments are directed towards apparatuses, methods, and systems associated with a storage reclamation manager that generates a command to reclaim storage locations to assist in management of a storage capacity of a primary storage device. In embodiments, the command is a trim command to inform the storage device of storage locations including invalid data. In embodiments, the command is generated during performance of operations associated with a write-back operation where a cache coupled with the processor stores a first portion of data and the primary storage device stores a corresponding second portion of data. In embodiments, the command is generated during or after a write-back operation of a third portion of data into the cache device. In embodiments, the command assists in reclamation of storage locations in which the second portion of data is stored, to assist in management of a storage capacity of the primary storage device. Additional embodiments may be described and claimed.

公开(公告)号：US20190235785A1

公开(公告)日：2019-08-01

申请号：US16381914

申请日：2019-04-11

Applicant: Intel Corporation

Inventor： Jason Akers ,  Chace Clark

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: Embodiments are directed towards apparatuses, methods, and systems associated with a storage reclamation manager that generates a command to reclaim storage locations to assist in management of a storage capacity of a primary storage device. In embodiments, the command is a trim command to inform the storage device of storage locations including invalid data. In embodiments, the command is generated during performance of operations associated with a write-back operation where a cache coupled with the processor stores a first portion of data and the primary storage device stores a corresponding second portion of data. In embodiments, the command is generated during or after a write-back operation of a third portion of data into the cache device. In embodiments, the command assists in reclamation of storage locations in which the second portion of data is stored, to assist in management of a storage capacity of the primary storage device. Additional embodiments may be described and claimed.